Semiconductor integrated circuit device and method for manufacturing the same

ABSTRACT

It is an object of the present invention to provide a technology of a semiconductor integrated circuitry that allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operated faster. In a method for manufacturing such a semiconductor integrated circuitry of the present invention, at first, gate electrodes  7  are formed via a gate insulating film  6  on the main surface of a semiconductor substrate  1 , and on side surfaces of each of the gate electrodes is formed the first side wall spacer  14  composed of silicon nitride and the second side wall spacer  15  composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area are opened connecting holes  19  and  21  in a self-matching manner with respect to the first side wall spacers  14  and are formed connecting portion connecting a conductor  20  to a bit line BL. In addition, in the N channel MISFETs Qn 1  and Qn 2 , and in the P channel MISFET Qp 1  in areas other than the DRAM memory cell area are formed high density N-type semiconductor areas  16  and  16   b , as well as a high density P-type semiconductor area  17  in a self-matching manner with respect to the second side wall spacers  15.

TECHNICAL FIELD

The present invention relates to semiconductor integrated circuitry andto a technology for manufacturing semiconductor integrated circuitry;and more particularly, the present invention relates to a technologyeffectively applicable for realizing higher integration and higherperformance of a DRAM (Dynamic Random Access Memory) or an electricallyreloadable nonvolatile memory, or for a highly integrated semiconductorcircuit provided with a logic circuit and a DRAM or an electricallyreloadable nonvolatile memory.

BACKGROUND OF THE INVENTION

There is a DRAM used as a semiconductor memory representing a largecapacity memory. The memory capacity of this DRAM is increasing more andmore, and, under the circumstances, it has become necessary to reducethe area occupied by the memory cells to improve the degree ofintegration of the DRAM.

However, the storage capacity of an information storing capacity element(capacitor) in DRAM memory cells must be fixed to a certain valueregardless of the generation when in taking the DRAM operation margin,software errors, etc. into consideration. Generally, it is known thatthe storage capacity cannot be reduced proportionally.

This is why there is now under development a capacitor structure thatcan secure a storage capacity necessary in a limited small occupationarea. As such a capacitor structure, for example, there has been adopteda three-dimensional capacitor, such as a so-called stacked capacitorcomposed of two-layer electrodes composed of polysilicon, etc. andstacked via a capacity insulating film.

A stacked capacitor is generally composed of capacitor electrodesdisposed in the upper layer of a memory cell selecting MISFET (MetalInsulator Semiconductor Field Effect Transistor). In this case, a smalloccupied area can secure a large storage capacity, as well as only asmall storage capacity, as needed.

As such a stacked capacitor structure, for example, there are aso-called capacitor over bit-line (hereafter, to be abbreviated as COB)structure, in which a capacitor is disposed over the bit-line, and acapacitor under bit-line (hereafter, to be abbreviated as CUB)structure, in which a capacitor is disposed under the bit-line.

In a DRAM having such a COB/CUB structure, capacitor connecting holesmust be formed so that a conductor film or a bit-line in each capacitorconnecting hole is not short-circuited with a word-line. Thus, theinterval between adjacent word-lines must be widened to cope withconnecting hole positioning failures. And, this hinders improvement ofthe degree of integration of elements, as well as a reduction of thechip sizes. In order to realize high integration, therefore, hightechnology of positioning and alignment, as well as process management,are needed.

In order to solve these problems and meet certain requirements, there isproposed a technology for forming capacitor connecting holes andbit-line connecting holes by etching in a self-matching manner withrespect to the word-lines by covering the top and side surfaces of theword-lines using an insulating material different in type from aninterlaminar insulating film, such as a nitride film, etc.

In the case of such a technology, when capacitor connecting holes andbit-line connecting holes are formed by etching, it is possible toprevent the word-lines from being exposed from the connecting holes,even when the connecting holes overlap the word-lines, since the nitridefilm around the word-lines functions as an etching stopper. Thus, theconnecting holes can be formed properly.

The technology for forming capacitor connecting holes and bit-lineconnecting holes in a self-matching manner with respect to theword-lines is disclosed in the official report of Unexamined PublishedJapanese Patent Application No. 9-55479.

Under the circumstances, the present inventor has examined thetechnology for forming the capacitor connecting holes and bit-lineconnecting holes in a self-matching manner with respect to theword-lines. The following technologies are not well-known, but have beenexamined by the present inventor. An outline of those technologies willbe described below.

The DRAM described above is formed in the following process flow. Atfirst, a conductor layer is formed on a semiconductor substrate via agate insulating film. On the conductor film there is deposited a firstnitride film. Then, the first nitride film and the conductor film arepatterned using the same mask to form gate electrodes of the memory cellselecting MISFET and gate electrodes of the peripheral circuit MISFET.At this time, the gate electrodes of plural memory cells disposed in therow direction of the memory cell array are formed unitarily and functionas a DRAM word line. Next, a low density semiconductor area is formedfor the memory cell selecting MISFET and the peripheral circuit MISFET,respectively, in a self-matching manner with respect to the memory cellselecting MISFET and the peripheral circuit MISFET, respectively. Then,a second nitride film is deposited on the semiconductor substrate andanisotropic etching is carried out to form nitride film side wallspacers on side walls of the gate electrodes of both the memory cellselecting MISFET and the peripheral circuit MISFET. Then, a high densitysemiconductor area is formed for the peripheral circuit MISFET in aself-matching manner with respect to the side wall spacers. Thereafter,on the semiconductor substrate there is deposited an interlaminarinsulating film composed of an oxide film, and bit-line and capacitorconnecting holes are opened in the memory cell area in a self-matchingmanner with respect to word-lines. This process for opening the bit-lineand capacitor connecting holes in this interlaminar insulating film isperformed on conditions to increase the etching selection ratio of thenitride film composing side walls to the oxide film composing theinterlaminar insulating film, so that the bit-line and capacitorconnecting holes can be formed without exposing the word-lines.

On the other hand, in order to improve the degree of integration of theDRAM memory cells, the interval between word-lines must be minimized.When the second nitride film is deposited on the word-lines disposed atminimized intervals up to a specified film thickness or more, everyspace between word-lines in the memory cell area is filled completelywith the second nitride film, so that the surface of the semiconductorsubstrate is not exposed even after anisotropic etching is carried outfor the nitride film to form side wall spacers. Otherwise, a problemthat the exposed area is very small and the contact resistance generatedbetween the exposed area and each bit-line or capacitor electrode isincreased significantly arises.

In addition, side wall spacers formed on side walls of the gateelectrodes of both the memory cell selecting MISFET and the peripheralcircuit MISFET determine the length of the low density semiconductorarea of the peripheral circuit MISFET having an LDD structure. And, whenthis side wall spacer is reduced in width, problems arise in that theshort channeling effect of the peripheral circuit MISFET becomesremarkable and the punched-through dielectric strength between sourceand drain is lowered. This is why the second nitride film for formingside wall spacers must have a thickness greater than a specified value.

In other words, in order to secure a specified performance of a MISFET,the LDD structure must be optimized. When the DRAM memory cell selectingMISFET is divided finely to reduce the width of the side wall spacer,the side wall spacer width must be greater than a specified value toprevent the high density semiconductor area of the peripheral circuitMISFET from being distributed over the low density semiconductor area.This means that the width of each side wall spacer has a lower limit.

On the other hand, when the memory array is divided finely, the intervalbetween gate electrodes, that is, the interval between adjacent memorycell selecting MISFETs is narrowed accordingly. Thus, every portion tobe connected in a self-matching manner is also reduced in width. Whensuch a connecting area is narrowed, the contact resistance in the areais also increased significantly. Thus, the side wall spacer must beminimized in width. Such a requirement conflicts with a requirement foroptimizing the LDD structure. And, in the worst case, when the LDDstructure is optimized, adjacent side wall spacers are overlapped in thememory array area so that self-matching connections are disabled.

Under the circumstances, it is an object of the present invention toprovide semiconductor integrated circuit technology for dividing DRAMmemory cells finely so as to be more highly integrated and to make theoperation faster in the semiconductor integrated circuitry provided witha DRAM.

It is another object of the present invention to provide a semiconductorintegrated circuit technology for dividing memory cells finely so as tobe more highly integrated and make the operation faster in thesemiconductor integrated circuitry provided with a DRAM and anelectrically reloadable nonvolatile memory.

It is still another object of the present invention to provide atechnology for realizing a high performance semiconductor integratedcircuit having a DRAM which exhibits excellent refreshingcharacteristics.

It is still another object of the present invention to provide atechnology for realizing a semiconductor integrated circuit that canprevent the element isolating area on the semiconductor substrate fromover-etching when opening the connecting holes to improve thereliability of the semiconductor integrated circuitry.

It is still another object of the present invention to provide atechnology for simplifying the method of manufacturing a semiconductorintegrated circuit provided with a DRAM and an electrically reloadablenonvolatile memory.

It is still another object of the present invention to provide atechnology for realizing a semiconductor integrated circuit, which candivide DRAM cells finely so as to be more highly integrated and improvethe reliability of the peripheral circuit MISFET.

It is still another object of the present invention to provide atechnology for forming connecting holes in a self-matching manner evenin a highly integrated DRAM memory cell area and to prevent the elementisolating area at the bottom of each of the connecting holes fromover-etching.

It is still another object of the present invention to provide atechnology for improving the connecting hole treatment margin when theconnecting holes are formed in a self-matching manner and for preventingthe element isolating area at the bottom of each connecting hole fromover-etching.

It is still another object of the present invention to provide atechnology for suppressing an increase in the number of processesrequired when the connecting holes are formed in a self-matching mannerand the element isolating area at the bottom of each connecting hole isprevented from over-etching.

It is still another object of the present invention to provide atechnology for integrating a semiconductor integrated circuit morehighly and for improving the refreshing characteristics of the DRAM andthe transistor characteristics of the memory cell area.

The above and other objects and novel features of the present inventionwill fully appear from the description provided by this specificationand from the accompanying drawings.

SUMMARY OF THE INVENTION

Of the various aspects of the present invention disclosed in thisspecification, representative ones will be summarized as follows.

(1) The semiconductor integrated circuit of the present inventioncomprises a first MISFET including gate electrodes formed on the mainsurface of a semiconductor substrate via a gate insulating film and asemiconductor area which is in contact with a channel area on the mainsurface of the semiconductor substrate under the gate electrodes; and asecond MISFET including gate electrodes formed on the main surface of asemiconductor substrate via a gate insulating film and a low densitysemiconductor area in contact with a channel area on the main surface ofthe semiconductor substrate under the gate electrodes and a high densitysemiconductor area formed outside the low density semiconductor area,wherein a cap insulating film is formed on top of the first and secondMISFET gate electrodes, first side walls composed of a first insulatingfilm are formed on side surfaces of the second MISFET gate electrodes,and second side walls composed of a second insulating film, which is ofa different material from that of the first insulating film, are formedoutside the first side walls. Then, a conductor portion connecting thefirst MISFET semiconductor area to a member formed in the upper layer ofthe first MISFET is formed in a self-matching manner with respect tothird side walls formed with the first insulating film, and the secondMISFET high density semiconductor is formed in a self-matching mannerwith respect to the second side walls formed with the second insulatingfilm.

According to the above-described semiconductor integrated circuitry,since the first and second insulating films are formed on side surfacesof the gate electrodes, the connecting portion connecting a memberformed in the upper layer of the first MISFET is formed in aself-matching manner with respect to the third side walls formed withthe first insulating film, and the second MISFET high densitysemiconductor area is formed in a self-matching manner with respect tothe second side walls formed with the second insulating film, the degreeof integration and the performance of the semiconductor integratedcircuitry can be improved significantly.

In other words, the third side walls formed with the first insulatingfilm can secure the self-matching properties of the conductor portionused to connect the first MISFET semiconductor area to the member formedin the upper layer of the first MISFET, while the second side wallsformed with the second insulating film can optimize the position of thehigh density semiconductor area necessary to form a so-called LDD of thesecond MISFET, so that the second MISFET can maintain a high performancesatisfactorily. In other words, the first insulating film may be, forexample, a silicon nitride film, which is a material having an etchingselection ratio for the silicon oxide film, which is a material ofgeneral interlaminar insulating films, and the second insulating filmmay be a silicon oxide film that can block implanted ions necessary forforming an LDD. And, the second insulating film does not disturbself-matching connection for the first MISFET. On the other hand, thefirst and second insulating films can function as effective spacers forforming the LDD. Consequently, as for the first insulating film, thereis no need to take any space into consideration when designing an LDDstructure and it is only necessary to make the second insulating filmthick enough to realize the self-matching connection. Thus, the secondinsulating film can be reduced in thickness to allow the first MISFET tobe integrated more highly. On the other hand, as for the secondinsulating film, there is no need to take the interval between gateelectrode wirings in the first MISFET forming area into consideration.Thus, side wall spacers can be formed with a film thickness sufficientto maintain the second MISFET performance, so that the performance ofthe second MISFET can be improved more significantly.

The first insulating film can be used for the first and third side wallspacers composed of a silicon nitride film formed on side surfaces ofthe gate electrodes, and the second insulating film can be used for thesecond side wall spacers composed of a silicon oxide film formed on sidesurfaces of the gate electrodes with a first side wall spacer disposedtherebetween, respectively.

The first insulating film can be a silicon nitride film formed on thesemiconductor substrate including side surfaces of the gate electrodes,and the second insulating film can be used for side wall spacerscomposed of a silicon oxide film formed on side surfaces of the gateelectrodes with a silicon nitride film disposed therebetween,respectively. In such a case, when the connecting holes are opened forconnecting each MISFET, the etching process can be divided into a firstetching process for etching a silicon nitride film and a second etchingprocess for etching a silicon nitride film, so that a silicon nitridefilm can be used as an etching stopper for the first etching process.When the etching process is divided into two stages in such a way,connecting holes can be opened surely in the first etching, andover-etching can be prevented in the second etching process.

Furthermore, the semiconductor integrated circuitry of the presentinvention includes an N channel MISFET and a P channel MISFET in thesecond MISFET and can have a C (Complementary) MISFET structure.According to such semiconductor integrated circuitry, a higherperformance and a lower power consumption can be realized due to theMISFET structure, so that it is possible to form not only DRAMperipheral circuits, but also logic circuits using the second MISFET.Thus, the semiconductor integrated circuitry can have memory and logiccircuits together.

(2) The semiconductor integrated circuitry of the present invention isas described in section (1), and the first MISFET is a DRAM selectingMISFET disposed in the DRAM cell memory array area and the member formedin the upper layer of the first MISFET is a DRAM storage capacitor or abit line.

According to the semiconductor integrated circuitry, the DRAM memorycell integration degree is improved and the performance of theperipheral circuits formed with the second MISFET is improved, so thatit is possible to realize a high speed high performance DRAM integratedcircuit.

In addition, phosphorus is doped in the selecting MISFET semiconductorarea as an impurity and at least arsenic can be doped in the low densityor high density semiconductor area of the N channel MISFET of the secondMISFET. In addition, the N channel MISFET can include the first Nchannel MISFET and a second N channel MISFET, and the first N channelMISFET can include an arsenic doped low density semiconductor area, aphosphorus doped high density semiconductor area, and a arsenic dopedhigh density semiconductor area. In addition, the first N channel MISFETcan include a semiconductor in which boron is doped in an area incontact with the high density semiconductor area under the low densitysemiconductor area, and the second N channel MISFET does not include anyboron doped semiconductor area.

When phosphorus is doped in the selecting MISFET semiconductor area asan impurity in such a way, the selecting MISFET dielectric strength canbe improved and the leakage current between the source and drain can bereduced to improve the refreshing characteristics of the DRAM.Furthermore, when arsenic is doped in both low density and high densitysemiconductor areas of the first N channel MISFET, the first N channelMISFET channel length can be shortened, and when phosphorus is doped inthe low density semiconductor area and arsenic is doped in the highdensity semiconductor area of the second N channel MISFET, thedielectric strength of the second N channel MISFET can be improvedsignificantly. Furthermore, since a boron-doped semiconductor area isformed in the first N channel MISFET so as to function as apunched-through stopper, the channel length can further be shortened,and since no punched-through stopper is provided in the second N channelMISFET, the dielectric strength of the MISFET can further be improved.

Furthermore, it can be expected that no silicide layer is formed on thesurface of the selecting MISFET semiconductor area and that a silicidelayer is formed on the surface of the high density semiconductor area.Since no silicide layer is formed on the surface of the selecting MISFETsemiconductor area, the leakage between channels can be suppressed toform a DRAM having excellent refreshing characteristics, and since asilicide layer is formed on the surface of the high densitysemiconductor area, the resistance in the second MISFET connecting holesand the sheet resistance of the semiconductor area can be reduced tomake the MISFET operation faster and improve the performance of thesemiconductor integrated circuitry.

The selecting MISFET gate insulating film can be thicker than the secondMISFET gate insulating film. Since the second MISFET gate insulatingfilm is thinned in this way, the second MISFET channel length can beshortened, and since the selecting MISFET gate insulating film isthickened in this way, the dielectric strength of the MISFET can beimproved to form a DRAM having excellent refreshing characteristics.Furthermore, when the second MISFET channel length is shortened, thesemiconductor integrated circuitry can increase the MISFET drivingcurrent and enable its performance to be higher and its operation to befaster.

(3) The semiconductor integrated circuitry of the present invention isas described in section (1), and the first MISFET gate can be a floatinggate type MISFET, where the insulating film is a tunnel insulating film.The floating gate type MISFET is disposed in the memory array area fornonvolatile memory cells including the gate electrodes, floating gates,and control gates formed on the floating electrodes via an insulatingfilm.

According to this semiconductor integrated circuitry, just like the DRAMdescribed in section (2), the memory array area for the nonvolatilememory cells can be highly integrated and the performance of theperipheral circuit MISFET of the nonvolatile memory composed of thesecond MISFET can be improved significantly.

The second MISFET gate insulating film can be thicker than the firstMISFET gate insulating film. Since the second MISFET gate insulatingfilm is thickened, the dielectric strength of the peripheral circuitMISFET of the nonvolatile memory driven with a general high voltage canbe increased more significantly.

(4) The semiconductor integrated circuitry of the present inventionincludes both the DRAM and the nonvolatile memory as described insections (2) and (3). In other words, the first MISFET includes both theselecting MISFET and the floating gate type MISFET.

According to this semiconductor integrated circuitry, the DRAM and thenonvolatile memory array area can be highly integrated and theperipheral or logic circuit area can also be highly integrated.

The DRAM bit line and the wiring formed in the upper layer of thefloating gate type MISFET can be formed in the same process.Consequently, the number of processes can be reduced.

The insulating films of the selecting MISFET, the floating gate typeMISFET, the peripheral circuit or logic circuit MISFET that drives theDRAM, and the peripheral circuit MISFET that drives the floating gatetype MISFET differ in thickness from each other, And, it can be expectedthat the gate insulating film of the peripheral circuit MISFET thatdrives the floating gate type MISFET is thicker than that of thefloating gate type MISFET, and the gate insulating film of the floatinggate type MISFET is thicker than that of the selecting MISFET, and theselecting MISFET gate insulating film is thicker than the gateinsulating film of the peripheral circuit or logic circuit MISFET thatdrives the DRAM. Consequently, the gate insulating films of theselecting MISFET, the floating gate type MISFET, and the peripheralcircuit or logic circuit MISFET that drives the DRAM, and the peripheralcircuit MISFET that drives the floating gate type MISFET, can beoptimized in thickness for each MISFET.

In the semiconductor integrated circuitry as described in any ofsections (1) to (4), it can be expected that a silicon nitride film isformed in the second MISFET formed area so as to cover the second MISFETand the semiconductor substrate.

According to this semiconductor integrated circuitry, since a siliconnitride film is formed in the peripheral circuit or logic circuit areaon the semiconductor substrate, the element isolating area can beprevented from over-etching even when connecting holes are formed in theelement isolating area on the semiconductor substrate. Thus, no leakageoccurs from between elements. And, accordingly, the semiconductorintegrated circuitry can prevent generation of defects, therebyimproving both reliability and performance.

(5) The method of manufacturing the semiconductor integrated circuitryof the present invention includes processes: (a) for forming a gateinsulating film on the main surface of a semiconductor substrate; (b)for forming gate electrodes and a cap insulating film on the gateinsulating film; (c) for forming a low density semiconductor area of thefirst and second MISFETs in a self-matching manner, respectively, withrespect to the gate electrodes; (d) for forming the first side wallspacers on side surfaces of each of the gate electrodes; (e) for formingthe second side wall spacers outside the first side wall spacers; (f)for forming a high density semiconductor area in a self-matching mannerwith respect to the second side wall spacers of the second MISFET; (g)for depositing an interlaminar insulating film composed a silicon oxidefilm all over the semiconductor substrate; (h) for etching theinterlaminar insulating film and the second side wall spacers andopening the connecting holes in a self-matching manner with respect tothe first side wall spacers of the first MISFET; and (i) for forming aconductor portion in each of the connecting holes.

Furthermore, the method of manufacturing the semiconductor integratedcircuitry of the present invention includes processes: (a) for forming agate insulating film on the main surface of a semiconductor substrate;(b) for forming gate electrodes and a cap insulating film on the gateinsulating film; (c) for forming a low density semiconductor area of thefirst and second MISFETs in a self-matching manner, respectively, withrespect to the gate electrodes; (d) for depositing a silicon nitridefilm all over the surface of the semiconductor substrate including theside surfaces of each of the gate electrodes; (e) for forming side wallspacers on side surfaces of the gate electrodes with a silicon nitridefilm formed therebetween; (f) for forming a high density semiconductorarea in a self-matching manner with respect to the side wall spacers ofthe second MISFET; (g) for depositing an interlaminar insulating filmcomposed of a silicon oxide film all over the semiconductor substrate;(h) for etching the interlaminar insulating film and the side wallspacers to form openings in a self-matching manner with respect to thesilicon nitride film, and etching the silicon nitride film at the bottomof each opening to open the connecting holes; and (i) for forming aconductor portion in each of the connecting holes.

According to the semiconductor integrated circuitry, it is possible toform a semiconductor integrated circuitry as described in section (1).

(6) In the process (c), the manufacturing method of the presentinvention can implant phosphorus in the first MISFET semiconductor areaand implant arsenic in at least one or more low density n-typesemiconductor areas of the second MISFET. According to thismanufacturing method, the dielectric strength of the first MISFET can beimproved, and when arsenic is implanted in the low density semiconductorarea of the second MISFET, the second MISFET channel length can beshortened.

Furthermore, in the process (a), both the first MISFET gate insulatingfilm and the second MISFET gate insulating film can be formed in thesame process. In such a case, the gate insulating film forming processcan be shortened and simplified.

Furthermore, the process (a) for forming an insulating film can includea process for forming the first gate insulating film in an area wherethe first and second MISFETs are formed, a process for removing thefirst insulating film selectively from the area where the second MISFETis formed, and a process for forming the second insulating film in anarea where the second MISFET is formed. When those additional processesare included in the process (a), since the first and second MISFET gateinsulating films can be formed differently in thickness from each other,and after the first gate insulating film is formed, the secondinsulating film is formed, the second gate insulating film can bethinner than the first gate insulating film.

The method of manufacturing the semiconductor integrated circuitryaccording to the present invention is as described in section (5), andthe gate insulating film can be a tunnel insulating film of the floatinggate type MISFET composing a nonvolatile memory and the process forforming gate electrodes can include a process for forming the floatinggate electrodes of the floating gate type MISFET and a process forforming the control gate electrodes of the floating gate type MISFET.According to the manufacturing method of the semiconductor integratedcircuitry, it is possible to form a nonvolatile memory in which thememory array area can be highly integrated and the performance of theperipheral circuit area can be improved significantly.

(8) The method of manufacturing the semiconductor integrated circuitryaccording to the present invention is as described in sections (5) or(6), and prior to the process (a), there are included a process forforming the tunnel insulating film of the floating gate type MISFETcomposing a nonvolatile memory on the main surface of the semiconductorsubstrate and a process for forming the floating gate electrodes of thefloating gate type MISFET on the tunnel insulating film.

According to the manufacturing method of the present invention, it ispossible to manufacture a semiconductor integrated circuit provided withboth a DRAM and a nonvolatile memory in which the memory array area ishighly integrated and the performance of the peripheral circuit area isimproved significantly.

The gate electrodes formed in the process (b) and the control gates ofthe floating gate type MISFET can be formed in the same process tosimplify the process.

Furthermore, the tunnel insulating film can be thicker than the gateinsulating film formed in the process (a).

(9) The method of manufacturing the semiconductor integrated circuitryis as described in sections (5) to (8), and prior to the process (g),there can be included a process for depositing the second siliconnitride film in the area where the second MISFET is formed, etching theinterlaminar insulating film in the area where the conductor portionconnecting the second MISFET to a member is formed in the upper layer ofthe second MISFET conditions determined so that an etching selectionratio can be taken for the second silicon nitride film to form openings,and furthermore etching the second silicon nitride film at the bottom ofeach opening to open connecting holes to form a conductor portion.

According to the manufacturing method of the present invention, sinceetching of the interlaminar insulating film is stopped by the secondsilicon nitride film, then the second silicon nitride film can bethinned much more than the interlaminar insulating film can be etched,over-etching will be sufficient if it is made up to ½ of the secondsilicon nitride film. And, even when connecting holes overlap on theelement isolating area on the semiconductor substrate, the elementisolating area can be prevented from over-etching. Consequently, aproper etching process margin can be secured, the element isolatingfunction of the element isolating area can be kept, and the performanceand reliability of the semiconductor integrated circuitry can besecured.

The second silicon nitride film and the silicon nitride film formed asthe first insulating film can be formed in the same process.

Hereunder, the effects to be obtained by the representative aspects ofthe invention as set forth above will be described briefly.

(1) The present invention can provide semiconductor integrated circuitrytechnology for dividing the memory cells of a DRAM or a nonvolatilememory finely so as to be integrated more highly and to make theoperation faster in a semiconductor integrated circuit provided with aDRAM or a nonvolatile memory.

(2) The present invention can provide semiconductor integrated circuitrytechnology for dividing memory cells finely so as to be integrated morehighly and make the operation faster in a semiconductor integratedcircuit provided with a DRAM or an electrically reloadable nonvolatilememory.

(3) It is possible to provide a technology for realizing a highperformance semiconductor integrated circuit with excellent DRAMrefreshing characteristics.

(4) It is possible to provide a technology for realizing a highlyreliable semiconductor integrated circuit that can prevent an elementisolating area on the semiconductor substrate from over-etching whenconnecting holes are opened.

(5) It is possible to simplify the manufacturing processes for asemiconductor integrated circuit provided with a DRAM and anelectrically reloadable nonvolatile memory.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a cross sectional view of the major portion of a semiconductorintegrated circuit representing a first embodiment of the presentinvention.

FIG. 2 is a top view of a DRAM in a memory cell area, included in thesemiconductor integrated circuit of the first embodiment of the presentinvention.

FIG. 3 is a block diagram of the semiconductor integrated circuitry inthe first embodiment of the present invention.

FIG. 4 is an equivalent circuit diagram of the DRAM included in thesemiconductor integrated circuitry in the first embodiment of thepresent invention.

FIGS. 5 to 25 are cross sectional or top views showing an example of howto manufacture the semiconductor integrated circuitry in the firstembodiment in the order of the processes.

FIGS. 48 and 49 are cross sectional views of another example of how tomanufacture the semiconductor integrated circuitry of the firstembodiment of the present invention in the order of the processes.

FIG. 26 is a cross sectional view of the major portion of asemiconductor integrated circuit representing a second embodiment of thepresent invention.

FIGS. 27 to 29 are cross sectional views showing a method ofmanufacturing the semiconductor integrated circuitry of the secondembodiment in the order of the processes.

FIG. 30 is a cross sectional view of the major portion of asemiconductor integrated circuit representing a third embodiment of thepresent invention.

FIGS. 31 to 33 are cross sectional views showing a method ofmanufacturing the semiconductor integrated circuitry of the thirdembodiment in the order of the processes.

FIG. 34 is a cross sectional view of the major portion of asemiconductor integrated circuit representing a fourth embodiment of thepresent invention.

FIG. 35 is an expanded cross sectional view of the areas C and D shownin FIG. 34.

FIG. 36 is a top view of an electrically reloadable batch erasure typenonvolatile memory, a so-called flash memory array area included in thesemiconductor integrated circuitry of the fourth embodiment.

FIG. 37 is an equivalent circuit diagram of the flash memory portion.

FIGS. 38 to 46 are top or cross sectional views showing a method ofmanufacturing the semiconductor integrated circuitry in the fourthembodiment in the order of the processes.

FIG. 47 is a cross sectional view of the major portion of asemiconductor integrated circuit representing a fifth embodiment of thepresent invention.

FIG. 50(a) is a cross sectional view of a memory cell area of a DRAMrepresenting a sixth embodiment of the present invention. FIG. 50(b) isa cross sectional view of a peripheral circuit area of the DRAM in thesixth embodiment.

FIG. 51 is a top view of the memory cell area of the DRAM in the sixthembodiment.

FIG. 52(a) is a cross sectional view taken along the line IIIa—IIIa inFIG. 51.

FIG. 52(b) is a cross sectional view taken along the line IIIb—IIIb inFIG. 51.

FIGS. 35 to 79 are cross sectional views showing a method ofmanufacturing the DRAM in the sixth embodiment in the order of theprocesses.

FIGS. 80 and 81 are cross sectional views showing a method ofmanufacturing a DRAM representing a seventh embodiment of the presentinvention.

FIGS. 82 to 84 are cross sectional views showing a method ofmanufacturing a DRAM representing an eighth embodiment of the presentinvention.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereunder, examples embodiments of the present invention will bedescribed with reference to the accompanying drawings. In all of thedrawings of the various embodiments, the same numerals will be used toidentify members having the same functions, and a redundant explanationthereof will be omitted.

(1st Embodiment)

FIG. 1 is a cross sectional view of the major portion of a semiconductorintegrated circuit representing an embodiment of the present invention.FIG. 2 is a top view of a DRAM memory cell area included in thesemiconductor integrated circuit of the first embodiment of the presentinvention. FIG. 3 is a block diagram of the semiconductor integratedcircuit of the first embodiment of the present invention. FIG. 4illustrates an equivalent circuit of a DRAM included in thesemiconductor integrated circuit of the first embodiment of the presentinvention.

The semiconductor integrated circuitry in the first embodiment of thepresent invention, as shown in the area A in FIG. 1, includes storagecapacity elements (capacitors) C2 and C3 for storing information andforming DRAM memory cells; selecting MISFETs Qs2 and Qs3 connected tothe storage capacity elements C2 and C3; and word lines WL1 and WL4adjacent to the selecting MISFETs Qs2 and Qs3.

The cross section of the DRAM shown in FIG. 1 is as seen on the I—I linein the top view of the DRAM memory cell area shown in FIG. 2. Thesemiconductor integrated circuitry in the first embodiment, as shown inthe area B in FIG. 1, includes an N channel MISFET Qn1, a P channelMISFET Qp1, and the second N channel MISFET Qn2 used to form peripheralcircuits other than DRAM memory cells, as well as other logicalcircuits.

The semiconductor integrated circuitry in the first embodiment, as shownin FIG. 3, is a microcomputer formed on a semiconductor substrate 1together with an information processing CPU; input and output ports; ananalog digital circuit ADC; a timer, as well as a logical circuit LG; aROM for storing OS, etc.; and a DRAM used as a memory. The circuits ofthe microcomputer are connected to each other via a bus BUS. The Nchannel MISFET Qn1 and the P channel MISFET Qp1 can be used for logicalconfiguration such as the information processing CPU.

As shown in the equivalent circuit in FIG. 4, a single bit memory cellis comprised of the storage capacity element C for storing informationand the selecting MISFET Qs (Qs2 and Qs3). The storage capacity elementC and the selecting MISFET Qs are connected serially. The gate electrodeof the selecting MISFET Qs is connected electrically to word lines WL(WKO, WL1, and WLn) and is formed integrally. The word line WL isconnected to a word line driver WD. One of the source or drain area ofthe selecting MISFET Qs is connected electrically to one of theelectrodes of the storage capacity element C. The other electrodes ofthe source or drain area of the selecting MISFET are connected to a bitline BL and the bit line BL is connected to a sense amplifier SA. Inthis way, the single bit memory cell is disposed at an intersectionpoint of the word line WL and the bit line BL. As will be describedlater, the word line WL is extended in a first direction and the bitline BL is extended vertically in a second direction.

The sense amplifier SA is not specified specially, but it can becomprised of the N channel MISFET Qn1 and the P channel MISFET Qp1. TheN channel MOSFET used to form the word line driver WD, as will bedescribed later, can be comprised of the N channel MISFET Qn2 containingdifferent impurities in a low density semiconductor area from those ofthe N channel MISFET Qn1. In addition, this N channel MISFET Qn2 is usedfor a circuit of a charger pump circuit, as well as input and outputports as needed, which are operated with a higher voltage than that ofthe N channel MISFET Qn1.

Next, each part of the configuration will be described with reference toFIG. 1, which represents a cross sectional view of the major portion ofthe semiconductor integrated circuit according to the first embodimentof the present invention.

The single bit memory cell is comprised of the storage capacity elementC for storing information (C2 and C3) and the selecting MISFET Qs (Qs2and Qs3). The selecting MISFET Qs is formed in a P-type well area 5formed on the main surface of the P-type semiconductor substrate 1. TheP-type well area 5 of the memory cell is separated electrically from theP-type semiconductor substrate in the N-type semiconductor area 3.Consequently, in order to prevent noises from other circuits mounted onthe same semiconductor substrate 1 and reduce the DRAM bit line storagecapacity, a substrate bias can be applied to the P-type well area 5,which is a channel area of the selecting MISFET Qs.

The selecting MISFET Qs is formed in an activating area 5 b limited by afield insulating film 2 in the P-type well area 5. The selecting MISFETQs is comprised of a P-type well area 5 (channel forming area); a gateinsulating film 6; a gate electrode 7; and a pair of low density N-typesemiconductor areas 9 forming source/drain areas, into which impuritiesare doped at a low density. To reduce the resistance, the gate electrode7 may be structured with multiple layers of a silicon film containingimpurities of phosphorus (P), etc. or a silicon film on which silicidesuch as tungsten silicide (WSi) or a metallic film such as tungsten (W)is formed.

The top of the gate electrode 7 is covered with a silicon nitride film8, and on the side surfaces of the gate electrode 7 and the siliconnitride film 8 are formed the first side wall spacers 14 composed ofsilicon nitride and the second side wall spacers 15 composed of siliconoxide are formed. The silicon nitride film 8 is formed so that the samepattern is also formed on the gate electrodes 7.

In the low density N-type semiconductor area 9, for example, phosphoruscan be doped as an impurity. Consequently, the strength of theelectrical field (strength of the electrical field at the end portion ofthe drain) between the end portion of the gate electrodes 7 and theP-type well area 5 can be lowered, and further it is possible to preventgeneration of defective crystallization when impurities are implanted toreduce the leakage current and extend the refreshing time.

As shown in FIG. 6 to be described later, the selecting MISFET Qs isseparated electrically from the memory cells (in units of a pair ofmemory cells) by a field insulating film 2 and the active area 5 b islimited by the field insulating film 2.

One low density N-type semiconductor area 9 of the selecting MISFET Qsis connected to an electric conductor 20 via connecting holes 19 and theelectric conductor 20 is connected to one of the electrodes of thestorage capacity element C for storing information.

The electric conductor 20 is formed in a self-matching manner withrespect to the first side wall spacers 14 composed of silicon nitride.In other words, the connecting holes 19 are formed in a self-matchingmanner with respect to the first side wall spacers 14 composed ofsilicon nitride and formed on side surfaces of the gate electrodes 7.Since the second side wall spacers 15 are formed with silicon oxide,which is the same material as that of the insulating film 18 to bedescribed later, and the second side wall spacers 15 and the insulatingfilm 18 are formed with a material whose etching rate is different fromthat of the first side wall spacers 14, the electric conductor 20 can beconnected to the low density N-type semiconductor area 9 in aself-matching manner with respect to the first side wall spacers 14. Inother words, when the insulating film 18 and the second side wallspacers 15 are to be etched, the first side wall spacers 14 are etchedunder more strict etching conditions than those of the silicon oxide.Consequently, when the connecting holes 19 are to be formed, theconnecting holes 19 are opened widely and a proper large margin issecured, so that the interval between gate electrodes 7 can be reducedto improve the degree of integration. This is because the electricconductor 20 is connected in a self-matching manner with respect to thefirst side wall spacers 14. In other words, as will be described withreference to FIG. 8, even when the interval between adjacent word linesin the second direction, that is, the interval between gate electrodes7, is reduced to improve the integrating degree, the connecting holes 19can be opened widely and the contact resistance of each hole can belowered. In addition, when the connecting holes 19 are formed bylithography, the margin of alignment in the second direction can bereduced, so that the interval in the second direction can be reduced.

In the first embodiment, the connecting holes 19 are formed so as not tobe positioned on top of the gate electrodes 7. On top of the gateelectrodes 7, however, a silicon nitride film 8 is also formed, so thatthe connecting holes 19 may be opened so as to be positioned on the gateelectrodes 7. Consequently, a larger margin of alignment can be secured.

The other low density N-type semiconductor area of the selecting MISFETQs is formed integrally with the bit line BL and is connected to anelectric conductor 22 via the connecting holes 21.

Just like the electric conductor 20, the electric conductor 22 is alsoformed in a self-matching manner with respect to the first side wallspacers formed with silicon nitride on side surfaces of the gateelectrodes 7. In addition, just like the connecting holes 19, theconnecting holes 21 which lead to the bit line BL may be extended so asto be positioned on top of the gate electrodes 7. Consequently, like theconnecting holes 19, the connecting holes 21 can be opened widely andtake a large margin of alignment. The interval between gate electrodes 7(interval between word lines WL) can thus be reduced to improve thedensity of integration. In other words, as will be described later withreference to FIG. 20, even when the interval between adjacent memorycell selecting MISFETs Qs in the second direction, that is, the intervalbetween gate electrodes, is reduced to improve the degree ofintegration, the connecting holes 21 can be opened widely and thecontact resistance of each hole can be lowered. And, when the connectingholes 21 are to be formed by lithography, the margin of alignment in thesecond direction can be reduced, so that the interval between gateelectrodes 7 in the second direction can also be reduced.

The electric conductors 20 and 22 may be formed with silicon containingimpurities, such as phosphorus, etc. or silicide, such as WSi to lowerthe resistance.

The storage capacity element C for storing information is composed ofelectric conductors 25 and 27 composing one of the electrodes (lowerelectrodes), a dielectric material 28 and upper electrodes 29 composingthe other electrodes. As will be described later with reference to FIG.22, the electric conductors 25 and 27 are connected to the electricconductor 20 via connecting holes 24 and are isolated electrically fromone of the respective electrodes of the other storage capacity element Cfor storing information. Each of the one electrodes is connected to onelow density N-type semiconductor area of one selecting MISFET Qscorresponding to the electrode. Each of the other electrodes of thestorage capacity element C for storing information are connectedelectrically to plural memory cells. In an area (not illustrated), forexample, those electrodes are connected to a plate potential generatorcircuit whose voltage is ½ of the supply voltage.

The electric conductors 25 and 27, and the upper electrodes 29 areformed with a silicon film containing impurities such as phosphorus toreduce, for example, the resistance thereof. The dielectric materialfilm 28 is formed with a laminated film composed of, for example, asilicon nitride film and a silicon oxide film, or a laminated filmcomposed of a tantalum oxide film, etc.

The N channel MISFET Qn1 is formed in the P-type well area 5 and iscomposed of: the P-type well area 5 (channel forming area); a gateinsulating film 6; gate electrodes 7; and a pair of low densitysemiconductor areas 10 forming a source and a drain. Under the lowdensity semiconductor areas 10 there is formed a P-type semiconductorarea 11 to obtain an N channel MISFET (short channel) whose gate isshorter than that of the N channel MISFET Qn1. The P-type semiconductorarea 11 functions as a so-called punched-through stopper of the MISFET.

Just like the DRAM selecting MISFET Qs, a silicon nitride film 8 isformed on the gate electrodes 7, and on side surfaces of the gateelectrodes 7, there are formed the first side wall spacer 14 made ofsilicon nitride and the second side wall spacers 15 made of siliconoxide. The high density N-type semiconductor area 16, as will bedescribed later, is formed in a self-matching manner with respect to thesecond side wall spacers 15 formed of silicon oxide. Since the highdensity N-type semiconductor area 16 is formed in a self-matching mannerwith respect to the second side wall spacers 15, the thickness of thesecond side wall spacers 15 can be optimized to improve the performanceof the N channel MISFET Qn1.

The low density N-type semiconductor area 10 is implanted, for example,with arsenic (As) as an impurity to obtain a long-gate and short-channelN channel MISFET. Since the thermal diffusion coefficient of arsenic issmaller than that of phosphorus, the horizontal diffusion of impuritycan be shortened. It is thus possible to obtain a long-gate andshort-channel N channel MISFET. In addition, since the thermal diffusioncoefficient is small, the density of the low density semiconductor area10 can be more greatly increased. The parasitic resistance can thus bereduced and a high performance N channel MISFET can be obtained. The lowdensity N-type semiconductor area 10 is formed in a self-matching mannerwith respect to the gate electrodes 7 and the silicon nitride film 8.

Under the low density semiconductor area 10 there is formed a P-typesemiconductor area 11 that functions as a punched-through stopper. Boron(B) is implanted into the area P-type semiconductor area 11 as animpurity. Since this P-type semiconductor area 11 is provided, theextension of a barrier layer can be suppressed, and accordingly theshort channel characteristics can be improved.

The P channel MISFET Qp1 is formed in the N type well area 4. The MISFETQp1 is composed of: the N type well area 4 (channel forming area); agate insulating film 6; gate electrodes 7, and a pair of low densityP-type semiconductor areas 12 forming a source and a drain. The lowdensity P-type semiconductor area 12 is formed between the channelforming area and the high density P-type semiconductor area 17. Underthe low density P-type semiconductor area 12 there is formed an N-typesemiconductor area 13 to obtain a short-gate and short-channel P channelMISFET, which can be obtained by shortening the gate length of the Pchannel MISFET Qp1. The N-type semiconductor area 13 functions as aso-called punched-though stopper of the MISFET. Just like the DRAMselecting MISFET Qs, a silicon nitride film 8 is formed on the gateelectrodes 7. On the side surfaces of both the gate electrodes 7 and thesilicon nitride film 8, the first side wall spacers 14 made of siliconnitride and the second side wall spacers 15 made of silicon oxide areformed. The high density P-type semiconductor area 17, to be describedlater, is formed in a self-matching manner with respect to the secondside wall spacers 15 made of silicon oxide. Since the high densityP-type semiconductor area 17 is formed in a self-matching manner withrespect to the second side wall spacers 15, the thickness of the secondside wall spacer 15 can be optimized to improve the performance of the Pchannel MISFET Qp1. Consequently, the high density P-type semiconductorarea 17 can be prevented from diffusion over the low density P-typesemiconductor area 12.

Boron is implanted into the low density P-type semiconductor area 12 asan impurity. Under the low density P-type semiconductor area 12 there isformed an N-type semiconductor area 13, which functions as apunched-through stopper. The N-type semiconductor area 13 is implantedwith arsenic or phosphorus as an impurity. Since the N-typesemiconductor area 13 is provided, the extension of the barrier layercan be suppressed and further the short channel characteristics can beimproved.

The N channel MISFET Qn2 is formed in the P type well area 5 and iscomposed of: the P type well area 5 (channel forming area); a gateinsulating film 6; gate electrodes 7; and a pair of low densitysemiconductor areas 10 b forming a source and a drain; and the highdensity N-type semiconductor area 16 b. The pair of low densitysemiconductor areas 10 b are formed between the channel forming area andthe high density N-type semiconductor area 16 b. Just like the DRAMselecting MISFET Qs, on the gate electrode 7 there is formed a siliconnitride film 8, and on the side surfaces of the gate electrodes 7 thefirst side wall spacer 14 made of silicon nitride and the second sidewall spacers 15 made of silicon oxide are formed. And, the low densitysemiconductor area 10 b is formed in a self-matching manner with respectto the gate electrodes 7 and the silicon nitride film 8. The highdensity N-type semiconductor area 16 b, to be described later, is formedin a self-matching manner with respect to the second side wall spacers15 composed of silicon oxide. Since the high density N-typesemiconductor area 16 b is formed in a self-matching manner with respectto the second side wall spacers 15, the high density N-typesemiconductor area 16 b can be prevented from diffusion over the lowdensity semiconductor area 10 b and the strength of the electrical fieldin the low density semiconductor area 10 b can be reduced. In addition,the thickness of each second side wall spacer 15 can be optimized so asto have a specified resistance value and to improve the performance ofthe N channel MISFET Qn2. In other words, even when the thickness of thesecond side wall spacer 15 is optimized to improve the performance ofthe N channel MISFET Qn2, the interval between word lines WL in thesecond direction in the memory cell array, that is, the interval betweengate electrodes of the selecting MISFET Qs, can be reduced and theconnecting holes 19 and 20 can be opened widely to take a large marginof alignment. Thus, the contact resistance of each hole can be lowered.

For example, phosphorus is implanted into the low density N-typesemiconductor area 10 b as an impurity, and under the low density N-typesemiconductor area 10 b a punched-through stopper of the P typesemiconductor area is not provided. Since the low density N-typesemiconductor area 10 b of the N channel MISFET Qn2 contains phosphorusas an impurity, the withstand voltage can be set higher than that of theN channel MISFET Qn1 in which the same low density semiconductor area 10is formed with arsenic. In addition, since no punched-through stopper isprovided, the withstand voltage can be set higher. This N channel MISFETQn2 can be used for a circuit such as a DRAM word line driver WD, acharge pump circuit, or an input/output port, which must operate with ahigher voltage than that of the N channel MISFET Qn1.

The semiconductor area forming each source/drain of the N channel MISFETQn1, the N channel MISFET Qn2, and the P channel MISFET Qp1 is connectedto a connecting member 31 connected to the first wiring 32, viaconnecting holes 30. The connecting member 31 can be formed in aself-matching manner with respect to the first side wall spacers 14composed of silicon nitride on side surfaces of the MISFET gateelectrodes 7 when necessary. In FIG. 1, the side surfaces of the gateelectrodes 7 mentioned here are the left connecting area of the Pchannel MISFET Qp1.

In addition, each line of the first wiring 32 is connected to aconnecting member 35 connected to the second wiring 36, via a connectinghole 34. Each line of the second wiring 36 is connected to a connectingmember 39 connected to the third wiring 40, via a connecting hole 38.And, on those first, second, and third wirings there is formed apassivation film 41 on which a bonding area 42 is formed.

The material of the connecting members 31, 35, and 39 for connectingupper and lower wirings is not specified specially, but may be composedof tungsten (W). The material of the wirings 32, 36, and 40 is notspecified specially, but may be composed of an integrated film oftitanium nitride (TiN) and aluminum (Al) containing copper (Cu).

Each line of the wirings 32, 36, and 40 is insulated by insulating films18, 23, 33, and 37, respectively, and the insulating films 18, 23, 33,and 37 can be formed with a silicon oxide film or a silicon oxide filminto which either of boron or phosphorus, or both of them, are doped.The passivation film 41 can be formed with a silicon oxide film or asilicon oxide film into which either of boron or phosphorus, or both ofthem, are doped, or a silicon nitride film formed on the film.

Next, a method of manufacturing the semiconductor integrated circuitryin the first embodiment will be described with reference to FIGS. 5 to25. FIGS. 5 to 25 are cross sectional or top views indicating a methodfor manufacturing the semiconductor integrated circuitry in the firstembodiment in the order of the processes.

At first, as shown in FIGS. 5 and 6, field insulating films 2 are formedin specified areas on the P type semiconductor substrate 1. The fieldinsulating films 2 can be formed with silicon nitride using the LOCOS(Local oxidation of Silicon) method that uses a well-known selectiveoxidation method or a shallow groove isolation method, which will beexplained briefly below.

The shallow isolation method forms a silicon oxide film (notillustrated) and a silicon nitride film sequentially on the main surfaceof a P type semiconductor substrate 1. Then, the silicon oxide film andthe silicon nitride film are removed with photo resist, etc. from thearea where the field ;insulating film 2 is formed. Thereafter, a 0.3 to0.4 μm groove is formed in the depth direction of the P typesemiconductor substrate 1. Then, a thermal silicon oxide film is formedon the side surfaces and at-the bottom surface of the groove using thesilicon nitride film as an oxidation mask. And, a silicon oxide film isdeposited all over the thermal silicon oxide film with the CVD (ChemicalVapor Deposition) method, any then the silicon oxide film is removedfrom the area except for the groove with the CMP (Chemical MechanicalPolishing) method or the dry etching method, silicon oxide embeddingselectively in the groove. The silicon oxide film is densified (thermaltreatment for densifying) with the CVD method in an acid atmosphere.Then, the silicon nitride film is removed, so that the field insulatingfilm 2 is formed with the shallow groove isolation method. The residualportions are formed as active areas 5 b.

Next, an N type semiconductor area 3 is formed as shown in FIG. 7. The Ntype semiconductor area 3 can be formed, for example, using photo resistas a mask and by ion implantation of phosphorus, under the conditions(accelerating energy cLf 500 to 1000 keV and a dosing amount of about1×10{circumflex over ( )}12 atoms/cm²) The phosphorus is implanted onceor a few times by changing the conditions each time. Thereafter,impurities of the area are activated with a thermal treatment of about1000° C. In this case, the thermal treatment can be performed for 20 to30 min in an atmosphere of nitrogen including about 1% of oxygen.Preferably, the RTA (Rapid Thermal Annealing) method that uses aninfrared light for heating should be used to finish the thermaltreatment within a short time to enable the distribution of impuritiesto be controlled.

Next, an N type well area 4 and a P type well area 5 are formed. The Ntype well area 4 can be formed, for example, using photo resist as amask and by ion implantation of phosphorus, which implantation isperformed once or a few times by changing the conditions each time,under the conditions (an accelerating energy of 300 to 500 keV and adosing amount of about 1×10³ atoms/cm²). The P type well area 5 can beformed, for example, using photo resist as a mask and byion-implantation of boron, under the conditions (an accelerating energyof 200 to 300 keV and a dosing amount of about 1×10¹³ atoms/cm²). Thephosphorus is implanted once or a few times by changing the conditionseach time. Thereafter, a thermal treatment of about 1000° C. isperformed to activate the impurities. In this case, the thermaltreatment can be performed for 20 to 30 min in an atmosphere of nitrogenincluding about 1% of oxygen. Preferably, the RTA (Rapid ThermalAnnealing) method should be used to finish the thermal treatment withina short time to enable the distribution of impurities to be controlled.

Then, as shown in FIGS. 8 and 9, the silicon oxide film is removed fromthe P type semiconductor substrate 1 and a clean gate insulating film 6is newly formed. A silicon oxide is formed with a thermal oxidationmethod of 700 to 800° C., then a gate insulating film 6 made of siliconoxide containing nitrogen by a thermal treatment in an atmosphere ofnitrogen oxide composed of NO or N₂₀ is formed. In the atmosphere of NO,the thermal treatment in the atmosphere of nitrogen oxide can beperformed at 900 to 1000° C. In the atmosphere of N₂₀, the thermaltreatment can be performed at 1000 to 1100° C. for 20 to 30 min,respectively. Otherwise, the RTA method can be used to finish thethermal treatment within a short time at 1000 to 1100° C. With thisthermal treatment, the phase boundary between the gate insulating film 6and the P type semiconductor substrate 1 is formed satisfactorily, sothat the gate insulating film 6 can be suppressed from degradation dueto the hot carrier generated by a MISFET operation. The reason why thisphase boundary is formed satisfactorily is based on the presumption thatSi-N binding that is stronger than the Si-O binding is formed on thephase boundary between the gate insulating film 6 and the semiconductorsubstrate 1.

The thickness of the gate insulating film 6 is set so that the maximumelectrical field becomes 5 MeV/cm or less in operation. For example,when in an operation at 3.3 V, the thickness can be set to 7 to 9 nm.When in an operation at 2.5 V, the thickness can be set to 5 to 7 nm,and when in an operation at 1.8 V, the thickness can be set to 4 to 5nm.

Next, the gate electrodes 7 and the silicon nitride film 8 are formedsequentially. Each gate electrode 7 is formed with a silicon filmcontaining impurities such as phosphorus or with a multi-layer structureformed with silicide such as WSi or a metal such as W is formed on asilicon film. Those conductor films are deposited all over the surfacewith the CVD method or spattering method. Then, a silicon nitride film 8is deposited all over the film with the CVD or plasma CVD method, and,for example, a silicon nitride film and a conductor film are patternedsequentially as specified using photo a resist as a mask. With this, thegate electrodes such as the DRAM memory cell selecting MISFET Qs, the Nchannel MISFET Qn1, the N channel MISFET Qn2, and the P channel MISFETQp1, as well as the word lines WL extending in the first direction areformed. The channel length of each gate electrode 7 is formed so as tobe 0.2 to 0.4 μm. On the gate electrodes 7 and the word lines WL thereis formed a silicon nitride film 8 so as to have the same flat pattern.

Channel impurities for controlling the MISFET threshold value (Vth) canbe implanted by ion implantation before the gate insulating film 6 isformed or after the gate electrodes 7 are formed.

Next, a low density N-type semiconductor area 9 of the selecting MISFETQs and a low density N-type semiconductor area 10 b of the N channelMISFET Qn2 are formed selectively as shown in FIGS. 10 and 11 using aphoto resist as a mask. The low density N-type semiconductor areas 9, 10b are formed by ion implantation of phosphorus at an acceleration energyof 20 to 40 keV and at a dosing amount of about 5×10¹³ atoms/cm². Thelow density N-type semiconductor areas 9, 10 b are formed by implantingimpurities in a self-matching manner with respect to the gate electrodes7 and the silicon nitride film 8. In other words, a low density N-typesemiconductor areas 9, 10 b are formed in a self-matching manner withrespect to the gate electrodes 7 and the silicon nitride film 8.

Next, the low density semiconductor area 10 of the N channel MISFET Qn1and the P type semiconductor area 11 under the area 10 are formedselectively using a photo resist as a mask. The low densitysemiconductor area 10 is formed, for example, by ion implantation ofarsenic at an acceleration energy of 20 to 40 keV and at a dosing amountof about 1×10¹⁴ atoms/cm². In this case, arsenic can be implanted at anangle of 30 to 50° to the side surface of each gate electrode 7 (at 30to 5° to the perpendicular of the P type semiconductor area), althoughthis is not specified specially. Consequently, the low densitysemiconductor area 10 is also formed under the gate electrodes 7, sothat the hot carrier resistant properties can be improved. The lowdensity N-type semiconductor area 10 is formed by implanting impuritiesin a self-matching manner with respect to the gate electrodes 7 and thesilicon nitride film 8. In other words, the low density semiconductorarea 10 is formed in a self-matching manner with respect to the gateelectrodes 7 and the silicon nitride film 8.

The P-type semiconductor area 11 is formed, for example, by ionimplantation of boron at an acceleration energy of 10 to 20 keV and adose of about 1×10¹³ atoms/cm². In this case, boron can be implanted atan angle of 30 to 50° to the side surface of each gate electrode (at anangle of 30 to 50° to the perpendicular of the P type semiconductorarea), although this is not specified specially. Consequently, the boroncan be supplied sufficiently under the low density semiconductor area10, that satisfactory short channel characteristics can be obtained.

Furthermore, the low density P-type semiconductor area 12 of the Pchannel MISFET Qp1 and the N-type semiconductor area 13 under the Qp1are formed. The low density P-type semiconductor area 12 is formed, forexample, by ion implantation of boron at an acceleration energy of 5 to10 keV and a dose of about 5×10¹³ atoms/cm². In this case, boron can beimplanted at an angle of 30 to 50° to the side surface of each gateelectrode (at an angle of 30 to 50° to the perpendicular of the P typesemiconductor area), although this is not specified specially. TheN-type semiconductor area 13 is formed, for example, by ion implantationof phosphorus at an acceleration energy of 50 to 80 KeV and a dose ofabout 1×10¹³ atoms/cm². In this case, boron can be implanted at an angleof 30 to 50° to the side surface of each gate electrode (at an angle of30 to 50° to the perpendicular of the P type semiconductor area).Consequently, the boron can be supplied sufficiently under the lowdensity P-type semiconductor area 12, that satisfactory short channelcharacteristics can be obtained.

Thereafter, impurities are activated by a thermal treatment about 850°.In this case, the thermal treatment is performed for 20 to 30 min in anatmosphere of nitrogen containing about 1% of oxygen. Preferably, theRTA method should be used to finish the thermal treatment about 1000° C.within a short time to control the distribution of impurities.

The thermal treatment can also be performed at 700 to 800° C. in anatmosphere of oxidation before each of the low density semiconductorareas is formed. Consequently, the end portion of each gate electrode 7that is thinned when in patterning can be reinforced, thus improving thewithstand voltage of each gate.

As shown in FIGS. 12 and 13, the first side wall spacers 14 composed ofsilicon nitride are formed on the side surfaces of the gate electrodes 7and each silicon nitride film 8. The first side wall spacers 14 can beformed by depositing a silicon nitride film all over the surface usingthe CVD or the plasma CVD method, and then etching the film withanisotropic dry-etching. The thickness of each first side wall spacer 14composed of silicon nitride should be 0.04 to 0.08 μm in thelongitudinal direction (the second direction) under the gate electrode7. Consequently, each gate electrode 7 is covered with the siliconnitride film 8 on its top surface and with the first side wall spacer 14composed of silicon nitride on its side surfaces. Thus, connecting holes19 and 21 to be explained later can be opened in a self-matching manner.In addition, since the thickness of the first side wall spacer 14 can bethinned to about 0.04 to 0.08 μm, the interval between gate electrodes 7of the selecting MISFET Qs in the second direction can be reduced toimprove the integrating degree of the semiconductor integrated circuitryof the present invention.

The first side wall spacers 14 composed of silicon nitride can also bethinned and the low density semiconductor area may be formed after thefirst side wall spacers 14 are formed. In this case, even shorterchannel characteristics can be obtained. In other words, as shown inFIG. 48, after the first side wall spacers 14 are formed, low densityN-type semiconductor areas 9, 10, and 10 b, as well as a low densityP-type semiconductor area 12 can be formed in a self-matching mannerwith respect to the first side wall spacers 14.

Next, as shown in FIGS. 14 and 15, the second side wall spacers 15composed of silicon oxide are formed on the side surfaces of the firstside wall spacers 14. The second side wall spacers 15 can be formed bydepositing a silicon oxide film all over the, surface using the CVD orplasma CVD method, and then etching the film with anisotropicdry-etching. The thickness (width) of each second side wall spacer 15should be greater than that of each first side wall spacer 14. The totalthickness t2 of the first side wall spacer 14 composed of siliconnitride and the second side wall spacer 15 composed of silicon oxideshould be 0.1 to 0.15 μm in the channel direction under the gateelectrodes 7. At this time, even when a second side wall spacer 15composed of silicon oxide fills the space between two gate electrodes 7of the selecting MISFET Qs in the second direction, no problem willarise, as will be described later. In other words, only a space t3 ofthe first side wall spacer 14 composed of silicon nitride is neededbetween them. In other words, the connecting holes 19 and 21 can beopened in a self-matching manner with respect to the first side wallspacers 14, so the intervals t3 of the first side wall spacers 14 in thesecond direction are assumed to be openings of the connecting holes 19and 21 respectively. In other words, the thickness t1 of the first sidewall spacer 14 can be minimized in the second direction until aspecified contact resistance is assumed in the intervals t3 of the firstside wall spacers 14.

Next, the high density N-type semiconductor area 16 of the N channelMISFET Qn1 and the high density N-type semiconductor area 16 b of the Nchannel MISFET Qn2 are formed as shown in FIG. 16. The high densityN-type semiconductor areas 16, 16 b of the N channel MISFET Qn1 and thehigh density N-type semiconductor area 16 b of the N channel MISFET Qn2can be formed, for example, by ion implantation by implanting arsenic atan acceleration energy of 20 to 60 keV and at a dose of about 1 to5×10{circumflex over ( )}15 atoms/cm². At this time, no high densitysemiconductor area is formed in the selecting MISFET Qs. Consequently,it is possible to suppress crystallization defects caused by ionimplantation when forming a high density semiconductor area, and preventa problem that the leakage current from a PN junction is increased toshorten the refreshing time.

Next, the high density P-type semiconductor area 17 of the P channelMISFET Qp1 is formed. The high density P-type semiconductor area 17 canbe formed, for example, by ion implantation of boron at an accelerationenergy of 10 to 20 keV and at a dose of about 1 to 5×10{circumflex over( )}15 atoms/cm². Thereafter, the impurities in the area are activatedby a thermal treatment at about 850° C., which treatment is performedfor 20 to 30 min in an atmosphere of nitrogen containing about 1% ofoxygen. Preferably, the RTA method should be used to finish the thermaltreatment at about 1000° C. within a short time to control distributionof the impurities.

Since the second side wall spacers 15 are provided and the high densitysemiconductor area can be formed with the optimal side wall spacerlength t2, high performance N channel MISFETs Qn1 and Qn2, as well as aP channel MISFET Qp1 can be obtained. On the other hand, in the memoryarray, the thickness t1 of the first side wall spacers 14 and theinterval t3 between the first side wall spacers 14 can be reduced andthe interval in the second direction can be minimized. In addition, theopening margin of the connecting holes 19 and 21 can be taken widely tolower the contact resistance.

Next, an insulating film 18 is formed as shown in FIGS. 17 and 18. Thefilm 18 is composed of a silicon oxide film or a silicon oxide film intowhich either or both of boron and phosphorus are doped. The insulatingfilm 18 is formed by depositing a silicon oxide film or a silicon oxidefilm into which one or both of boron and phosphorus are doped all overthe surface, for example, the CV-D or plasma CVD method, and then thefilm is smoothed using the reflowing method or the CMP method so thatthe height from the surface of the substrate is smoothed uniformly.

Furthermore, connecting holes 19 are formed so as to be connected to theone side electrodes of the storage capacity element C for storinginformation, for the DRAM memory cells. The connecting holes 19 areformed by dry-etching under the conditions determined so that theselection ratio of the silicon nitride film 8 on the gate electrodes 7and the first side wall spacers 14 composed of silicon nitride to thesecond side wall spacers 15 composed of silicon oxide and the insulatingfilm 18 composed of silicon oxide is set to be large. In other words,the etching conditions are set so that the etching speed (capacity) ofthe silicon nitride is slower and the etching speed (capacity) of thesilicon oxide is faster. Such etching is possible when performedtogether with Ar spattering performed for the mixed gas of, for example,C₄F₈ and O₂. Etching is carried out under conditions to allow theconnecting holes 19 to be opened in a self-matching manner with respectto the first side wall spacers 14. In other words, since lightlithography technology is used to form the connecting holes 19, themargin of alignment in the second direction can be reduced and finepitches can be assumed in the second direction.

Furthermore, a polycrystal silicon film containing impurities such asphosphorus is formed all over the semiconductor substrate 1 to lower theresistance. Then, anisotropic etching is performed to remove thepolycrystal silicon film except for the connecting holes 19 to form anelectric conductor 20 in each of the connecting holes 19.

Thereafter, an insulating film (silicon oxide film, not illustrated)isdeposited to cover the electric conductor 20.

Next, connecting holes 21 to be connected to the DRAM memory cell bitlines BL are formed as shown in FIGS. 19 and 20. Dry etching isperformed to form the connecting holes 21 under conditions in which alarge selection ratio of silicon nitride to silicon oxide is taken, justlike the connecting holes 19. Consequently, each of the connecting holes21 can be opened in a self-matching manner with respect to the firstside wall spacer 14. Thus, just like the connecting holes 19, when thelight lithography is used to form the connecting holes 21, the margin ofalignment in the second direction can be reduced and fine pitches ofmembers can be assumed in the second direction.

Furthermore, a silicon film containing impurities such as phosphorus ora silicide film such as WSi is formed to lower the resistance. Then, anelectric conductor 22 is formed in each connecting hole 21 using a photoresist as a mask and is patterned so that the electric conductor 22 isextended vertically (to second direction) to the word line WL to serveas a bit line BL.

Next, as shown in FIGS. 21 and 22, an insulating film 23 composed ofsilicon oxide or silicon oxide into which one or both of boron andphosphorus are doped is formed. The insulating film 23 is formed justlike the insulating film 18 using, for example, the CVD or plasma CVDmethod so that a silicon oxide film or a silicon oxide film in which oneor both of boron and phosphorus are doped is deposited all over the surface, and then the film is flattened using the reflowing or CMP method sothat the height from the surface of the substrate 1 is smootheduniformly. Then, connecting holes 24 are formed so as to be connected toone of the electrodes of the storage capacity element C for storinginformation DRAM memory cells. The connecting holes 24 are dry-etched toform holes reaching the electric conductors 20. Such etching is possiblewhen performed together with Ar spattering carried out with a mixed gasof CF₄ and CHF₃.

Furthermore, electric conductors 25 are formed. The electric conductors25 are used as one of the electrodes of the storage element C forstoring DRAM memory cell information. Each electric conductor is formedwith a polycrystal silicon film containing impurities such asphosphorus, etc. or a silicide film such as WSi, etc. to reduce theresistance. Then, an insulating film 26 composed of, for example,silicon oxide, is formed and an electric conductor 25 is formed in eachconnecting hole using a photo resist as a mark. And, both the insulatingfilm 26 and the electric conductors 25 are patterned so as to be used asone of the electrodes of the storage element C for storing information.

As shown in FIG. 23, a polycrystal silicon film containing impuritiessuch as phosphorus or a silicide film such as WSi is formed to lower theresistance. Then, anisotropic dry etching is performed to form electricconductors 27 connected to the electric conductors 25 on the sidesurfaces of each insulating film 26. The electric conductors 25 and 27are used to form one of the electrodes of the storage capacity element Cfor storing information.

As shown in FIG. 24, after the insulating film 26 is removed, adielectric material film 28 and upper electrodes 29 are formedsequentially for the storage capacitor element C for storinginformation. The dielectric material film 28 is formed with a laminatedfilm composed of silicon oxide and silicon nitride or a tantalum oxide(Ta₂O₃) film. The upper electrodes 29 are formed with a polycrystalsilicon film containing impurities such as phosphorus or a silicide filmsuch as WSi to lower the resistance.

As shown in FIG. 25, connecting holes 30 are formed. The connectingholes 30 are used to connect the first wiring 32 to gate electrodes or asemiconductor area. Just like the connecting holes 19 and 21, theconnecting holes 30 are formed under conditions where a large selectionratio is attained for the silicon nitride 8 and the first side wallspacers 14 composed of silicon nitride to the second side wall spacers15 composed of silicon oxide and the insulating film 8 composed ofsilicon oxide. Then, a connecting member 31 is formed in each connectinghole 30. The connecting member 31 is formed by forming a titanium (Ti)film of 10 to 50 μm in thickness and titanium nitride (TiN) film ofabout 100 nm in thickness by the spattering method, and then removingthe tungsten film from areas other than the connecting holes 30 usingdry etching or the CMP method.

Furthermore, the first wiring 32 is formed. The first wiring can beformed with a laminated film made of a titanium nitrate (TiN) and analuminum (AL) film containing copper (Cu).

Finally, an insulating film 33, connecting holes 34, connecting members35, the second wiring 36, an insulating film 37, connecting holes 38,connecting members 39, and the second wiring 40 are formed sequentially.The insulating films 33 and 37 are formed just like the insulating film23. The connecting holes 34 and 38 are formed just like the connectingholes 30. The connecting members 35 and 39 and the second and thirdwirings 36 and 40 are formed just like the connecting members 31 and thefirst wiring 32. And, a silicon nitride or a laminated passivation film41 composed of silicon oxide is formed under the silicon nitride by theCVD method, and then a bonding area 42 is formed almost to complete themanufacturing of the semiconductor integrated circuitry shown in FIG. 1.

(2nd Embodiment)

FIG. 26 is a cross sectional view of the major portion of asemiconductor integrated circuitry representing another embodiment ofthe present invention.

The semiconductor integrated circuitry in the second embodiment is thesame as that in the first embodiment except that a silicon nitride film104 is formed on the N channel MISFET Qn1, the N channel MISFET Qn2, andthe P channel MISFET Qp1, and this silicon nitride film 104 is used asan etching stopper for forming connecting holes 30. Thus, since otherstructural features are the same as those in the first embodiment, anexplanation thereof will be omitted. And, since a silicon nitride film104 is provided in the semiconductor integrated circuitry in this secondembodiment, even when some of the connecting holes 30 overlap the fieldinsulating film 2, as shown on the right side of the P channel MISFETQp1 in FIG. 26, the field insulating film 2 is prevented fromover-etching when the connecting holes 30 are opened. Leakage currentand other problems to be caused by over-etching can thus be suppressed,thereby maintaining the performance and reliability of the semiconductorintegrated circuitry.

Hereunder, a method of manufacturing the semiconductor integratedcircuitry in the second embodiment will be described with reference toFIGS. 27 to 29. FIGS. 27 to 29 are cross sectional views indicating howto manufacture the semiconductor integrated circuitry of the secondembodiment in the order of the processes. Just like the firstembodiment, at first, the selecting MISFET Qs, the N channel MISFETs Qn1and Qn2, and the P channel MISFET Qp1 are formed, and then a siliconnitride film 104 is deposited on the N channel MISFETs Qn1 and Qn2, andthe P channel MISFET Qp1 with a thickness of about 50 nm . Then, thesilicon nitride film 104 masked with photo resist is not removed byetching except for at least the area where the connecting holes 19 and21 of the DRAM memory cells are formed. (FIG. 27)

Thereafter, just like in the first embodiment, the insulating film 18,the bit lines BL, and the storage capacity element C for storinginformation are formed. Then, when the connecting holes 30 are opened,the first stage etching is performed (FIG. 28). In this first stageetching, etching selection ratio is set so that the silicon oxideetching is faster than the silicon nitride etching, so to speak, underthe condition of a high etching selection rate. Consequently, theconnecting holes 30 can be opened surely up to the surface of thesilicon nitride 104. In addition, in this first stage etching, since thesilicon nitride film 104 functions as an etching stopper, the etchingcan be performed sufficiently to take a larger process margin withoutconsidering the peril of over-etching.

Next, the second stage etching is performed for the silicon nitride film104 at the bottom of each connecting hole 30 (FIG. 29). This secondstage etching is performed under conditions for etching silicon nitride,and there is no need to take an etching selection ratio for the siliconoxide. The etching at this time is to be a little deeper than thethickness of the silicon nitride film 104. For example, the etchingdepth is to be 110 to 130% of the thickness of the silicon nitride film104. Such etching is possible when performed together with AR spatteringwith a mixed gas of CF4 and CHF3. As a result, the field insulating film2 is hardly etched. This prevents the bottom of each etched connectinghole 30 from becoming deeper than the semiconductor area which forms asource and a drain. In other words, the silicon nitride film 104 isthinned sufficiently with respect to the field insulating film 2, sothat even when the silicon nitride film 104 is over-etched, the fieldinsulating film 2 is etched only by less than a half of the siliconnitride 104 in thickness, and the over-etching causes no problem to theprocesses.

Since the second stage etching is performed using such a silicon nitridefilm 104, the connecting holes 30 can be opened surely with an enoughprocess margin. The performance and reliability of the semiconductorintegrated circuitry can thus be maintained.

Hereafter, the manufacturing method of the second embodiment is entirelythe same as that of the first embodiment, thus an explanation thereofwill be omitted here.

(3rd Embodiment)

FIG. 30 is a cross sectional view of the major portion of asemiconductor integrated circuitry representing another embodiment ofthe present invention.

The semiconductor integrated circuitry in the third embodiment is thesame as that in the first and second embodiments except that a silicidelayer 105 is formed on the semiconductor areas except for at least thelow density N-type semiconductor area which forms the source and thedrain of the DRAM memory cell selecting MISFET Qs. In addition, in thisthird embodiment, a silicon nitride film 104 is also provided just likein the second embodiment. Consequently, the parasitic resistance of thesemiconductor area which forms the sources and the drains of the MISFETsQn1, Qn2, and Qp1 can be reduced to improve the performance of theMISFET Qn1, Qn2, and Qp 1 significantly without increasing the leakagecurrent from DRAM memory cells.

Next, a method of manufacturing the semiconductor integrated circuitryof the third embodiment will be described with reference to FIGS. 31 to33. FIGS. 31 to 33 are cross sectional views showing the manufacturingmethod of the present invention.

At first, just like the first embodiment, the high density N-typesemiconductor areas 16 and 16 b, and a high density P-type semiconductorarea 17 shown in FIG. 16 are formed. Then, an insulating film 106 isformed and the film 106 is removed by etching using a photo resist as amask except for at least the area of the DRAM memory cells (FIG. 31).When an insulating film exists on the semiconductor area before theinsulating film 106 is formed, the insulating film 106 is not formed,and instead, the insulating film mentioned above is removed selectively.

Next, a metallic film 107 composed of titanium (Ti) or cobalt (Co) isdeposited all over the surface using the spattering method (FIG. 32).Then, the first silicide reaction is performed in an inactive atmosphereat about 500° C., and then non-reacted portions of the metallic film 107except for the semiconductor area are removed. Thereafter, in aninactive atmosphere at about 700 to 900° C., the second silicidereaction is performed to reduce the resistance and form a silicide layer105 (FIG. 33). A silicide layer 105 is thus formed on the semiconductorarea which forms the sources and the drains of the MISFET Qn1, Qn2, andQp1 except for the low density N-type semiconductor area 9 forming thesource and the drain of the DRAM memory cell selecting MISFET Qs. Nosilicide layer 105 is needed on the semiconductor area forming sourcesand drains of the output circuit output MISFET and the input protectionMISFET.

Thereafter, the processes are the same as those shown in FIG. 27 in thesecond embodiment, and so an explanation thereof will be omitted here.

(4th Embodiment)

FIG. 34 is a cross sectional view of the major portion of asemiconductor integrated circuit representing in another embodiment ofthe present invention.

In the semiconductor integrated circuitry in the fourth embodiment, aflash memory is used as a ROM in the manner as shown in the blockdiagram in FIG. 3, which illustrates the first embodiment of the presentinvention. In FIG. 34, areas A and B are the same as those in the firstembodiment. Thus, an explanation for those items will be omitted here.

FIG. 35 is an expanded view of the areas C and D shown in FIG. 34. FIG.36 is a top view of the memory array area of an electrically reloadablebatch erasure type volatile memory, that is, a flash memory included inthe semiconductor integrated circuit of the fourth embodiment. FIG. 37is an equivalent circuit diagram of the flash memory portion. Hereunder,an explanation of this embodiment will be made with reference to FIGS.35 to 37.

In the flash memory of this fourth embodiment, a single bit memory cellis composed of: a tunnel insulating film 202; floating gate electrodes203; an interlaminar insulating film 204; control gates 7 formedunitarily with word lines; P type well areas 5 (channel forming areas);and a floating gate MISFET Qf having a pair of N type semiconductorareas forming sources and drains.

Just like the N channel MISFET Qn1 in the first embodiment, the sourceof the floating gate type MISFET Qf is formed with a low density N-typesemiconductor area 10 and a P-type semiconductor area 11 formed underthe area 10, and a high density N-type semiconductor area 16. The drainof the floating gate type MISFET Qf is formed with a high density N-typesemiconductor area 205. The thickness of the tunnel insulating film 202is set to 9 to 10 nm. The high density N-type semiconductor area 205 hasa impurity density higher than that of the low density N-typesemiconductor area 10 and has a high impurity density sufficient toreduce a depression of the surface of the high density N-typesemiconductor area 205 under the floating gate electrodes 203 wheninformation is written.

The drain of the floating gate type MISFET Qf is connected to the firstwiring 32 via a connecting hole 30. The first wiring 32 forms sub-bitlines subBL in the fourth embodiment. A memory cell composed of 16 to 64bits is connected to a sub-bit line subBL and to the main bit line BLcomposed of the second wiring 36 via the selecting MISFET Qs. In otherwords, the flash memory in this fourth embodiment is divided into blocksby the selecting MISFET Qsf The block selecting lines tWL1 and tWL2 areformed unitarily with the gate electrodes 203 of the selecting MISFETQsf.

The memory cell source is connected to the source line SL via aconnecting hole 21. The source is also connected to the source line BSLshared by all the divided blocks.

The selecting MISFET Qsf selects a block. In other words, the potentialof the main bit line BL is supplied to memory cells via the selectingMISFET Qsf As shown in FIG. 36, the word lines MWL (7), the blockselection lines TWL1 and tWL2, and the source lines SL are extended inthe first direction. The sub-bit lines subBL (32) are extended in thesecond direction.

The selecting MISFET Qsf is composed of: a gate insulating film 201;floating gate electrodes 203; gate electrodes 203 disposed in the samelayer as the floating gate electrodes 203; and a high density N- typesemiconductor area 205 composed of a source and a drain. In FIG. 34,each gate electrode has a two-layer structure, but in an area (notillustrated), a control gate electrode 7 formed unitarily with a wordline is connected to the first wiring 32 and is shunted by the thirdwiring 40. The thickness of the gate insulating film 201 is set to about20 nm.

The connecting holes 21 and 30 communicating with the source and thedrain of the floating gate type MISFET Qf, as shown in FIGS. 45 and 46to be described later, are formed in a self-matching manner with respectto the first side wall spacers 14 composed of silicon nitride just likethe connecting holes 19 and 21 in the first embodiment. Those memorycells are isolated by the N type semiconductor area 3 so that writingand erasing to be described below can be performed.

Writing data in the flash memory of the present invention is forming bydischarging electrons from the floating gate electrodes 203 and loweringthe threshold value (Vth). In other words, a negative voltage of about9V is applied to the control electrodes 7. Then, a positive voltage ofabout 7V is applied to the drain so that electrons are discharged fromthe floating gate electrodes 203 to the high density N-typesemiconductor area 205, which is a drain, through the FN (FowlerNordheim) tunnel via the tunnel insulating film to lower the thresholdvalue (Vth).

To erase data, electrons are charged in the floating gate electrodes 203to increase the threshold value (Vth). In other words, a positivevoltage of about 9V is applied to the control gate electrodes 7. Then, anegative voltage of about 9V is applied to the source and the P typewell area 5 to charge electrons from an inverse layer formed in achannel area into the floating gate electrodes through the FN tunnel viathe tunnel insulating film. Thus, the threshold value is increased.

The N channel MISFET Qn3 and the P channel MISFET Qp2 are used for acircuit for writing and erasing data in and from the flash memory.

With the semiconductor integrated circuitry, even when a flash memory isincluded in the circuitry, the first and second side wall spacers 14 and15 are formed to divide the memory cell area finely, so that the LDD canbe optimized for the peripheral circuit areas MISFET Qn1, Qn2, Qn3, Qp1,and Qp2. The fine division and performance of the semiconductorintegrated circuitry can thus be improved.

Next, a method of manufacturing the semiconductor integrated circuitaccording to this fourth embodiment will be explained with reference toFIGS. 38 to 46. FIGS. 38 to 46 are cross sectional or top viewsillustrating various stages of manufacture of the semiconductorintegrated circuitry in this fourth embodiment in order of theprocesses.

At first, just like the first embodiment, the field insulating film 2;the N type semiconductor area 3; the N type well area 4; and the P typewell area 5 are formed. FIG. 38 is a top view of flash memory areasafter the field insulating film 2 is formed.

Next, as shown in FIGS. 39 and 40, a gate insulating film 201 is formedusing a thermal oxidation method. Then, the film 201 except for theselecting MISFET Qsf, the N channel MISFET Qn3, and the P channel MISFETQp2 is removed. Then, a tunnel insulating film 202 is formed using athermal oxidation method. Since the tunnel insulating film 202 is formedafter the gate insulating film 201 is removed, the tunnel insulatingfilm 202 which is thinner than the gate insulating film 201 can beformed easily. Thereafter, the flash memory floating gate electrodes203, as well as electric conductors 206 used as the floating gateelectrodes 203 of the selecting MISFET Qsf, the N channel MISFET Qn3,and the P channel MISFET Qp2 are formed. The electric conductors 206 areformed with a silicon film in which impurities such as phosphorus areimplanted to lower the resistance. Thereafter, the silicon film maskedwith photo resist is patterned.

As shown in FIG. 41, the floating gate electrodes 203 of the flashmemory and an interlaminar insulating film 204 is formed between controlelectrodes 7. The interlaminar insulating film 204 is formed with amulti-layer film formed by laminating a silicon oxide film and a siliconnitride film sequentially. Then, the interlaminar insulating film 204 isselectively removed from the areas where the DRAM memory cell selectingMISFET Qs, the N channel MISFET Qn1, the N channel MISFET Qn2, and the Pchannel MISFET Qp1 are formed. Then, the silicon nitride film on theinterlaminar insulating film 204 is used as an oxidation resistance maskto form a gate insulating film 6 just like in the first embodiment.

Next, as shown in FIGS. 42 and 43, the control gate electrodes 7 and thesilicon nitride film 8 on the electrodes 7 are formed, and then the film8 is patterned using a photo resist as a mask. The floating gateelectrodes 203 of the flash memory and the control gate electrodes 7 arethus formed.

Hereafter, the processes are almost the same as those shown in FIG. 10in the first embodiment. In other words, as shown in FIG. 44, the firstand second side wall spacers 14 and 15 are formed in the DRAM memorycell area, and at the same time, they are formed in the flash memorycell area in the same way. The number of processes can thus be reduced.

Next, just like in the first embodiment, an insulating film 18 isformed, and then connecting holes 21 are formed as shown in FIG. 45.

Next, an insulating film 23 is formed, then connecting holes 30 areformed as shown in FIG. 46.

The connecting holes 21 and 30, just like the connecting holes 19 and 21in the first embodiment, are formed in a self-matching manner withrespect to the first side wall spacers 14 composed of silicon nitride,so that the interval t3 between word lines WL (gate electrodes 7) in thesecond direction, the interval t3 between word lines WL (gate electrodes7) and block selecting lines tWL1 and tWL2, and the interval t3 betweenblock selecting lines tWL1 and tWL2 can be reduced finely in the seconddirection.

In addition, since the margin of alignment in the second direction canbe reduced, the interval between elements in the second direction can bereduced finely. In other words, the interval between memory cells in thesecond direction can be reduced significantly, enabling thesemiconductor integrated circuitry of the present invention to beintegrated much more finely.

Next, the first wiring 32 is formed just like in the first embodiment.Consequently, DRAM memory cell bit lines BL and flash memory sourcelines SL can be formed in the same process, so the process can beshortened and simplified.

According to the method of manufacturing the semiconductor integratedcircuitry of the fourth embodiment, the circuitry can be manufacturedjust like the semiconductor integrated circuitry provided with a flashmemory in the first embodiment, and the memory cell array can beintegrated very finely in the flash memory. In addition, the thicknessof the gate insulating film can be varied according to the MISFETrequirement.

Needless to say, the silicon nitride film 104 or the silicide layer 105described in the second and third embodiments may be included in themethod of manufacturing the semiconductor integrated circuitry of thisfourth embodiment. In this fourth embodiment, needless to say, thesemiconductor integrated circuitry is provided with both DRAM and aflash memory, but this invention can also apply to a semiconductorintegrated circuit provided only with a flash memory.

(5th Embodiment)

FIG. 47 is a cross sectional view of the major portion of asemiconductor integrated circuit representing in another embodiment ofthe present invention. The semiconductor integrated circuitry in thisfifth embodiment is the same as that in the first embodiment except forthe fact that a silicon nitride film (the first side wall spacer) 207 isformed instead of the first side wall spacers 14. Other structuralfeatures are entirely the same as those in the first embodiment, and soon explanation thereof will be omitted here. In the semiconductorintegrated circuitry in this fifth embodiment, a silicon nitride film(the first side wall spacers) 207 of t1 in thickness is provided, sothat the degree of integration of the memory cell area can be improvedand the MISFET LDD structure other than the memory cell area can beoptimized due to the second side wall spacers 15, thereby to improve theperformance of the semiconductor integrated circuitry just like in thefirst embodiment.

In the method of manufacturing the semiconductor integrated circuitry ofthis fifth embodiment, the process for forming the first side wallspacers 14 shown in FIG. 12 in the first embodiment is replaced with aprocess for depositing a silicon nitride film 207 all over thesemiconductor substrate 1. Consequently, the isotropic etching and otherprocesses are omitted, making it possible to simplify the manufacturingmethod significantly. In the processes for opening the connecting holes19 and 21, however, the second stage etching is needed, as described inthe second embodiment. The number of processes is thus increased, butthe semiconductor substrate 1 exposed at the bottoms of the connectingholes 19 and 21 can be prevented from over-etching, so that the contactreliability is improved.

Various embodiments of the present invention have been described indetail above, but the present invention is not limited only to thoseembodiments. Needless to say, they can be varied as long as thesubstance of the present invention is not exceeded.

For example, in the first to fifth embodiments, a complementary MISFETis used to form peripheral or logic circuits, but only an N channelMISFET or P channel MISFET may be used to form the peripheral circuits.

In addition, in the first to fifth embodiments, the thickness of thegate insulating film of the DRAM memory cell area selecting MISFET Qs isequal to the thicknesses of the gate insulating films of the N channelMISFET Qn1, Qn2, and the P channel MISFET Qp1, but those insulatingfilms may differ in thickness from each another. More particularly, whenthe gate insulating films of the N channel MISFET Qn1, Qn2, and the Pchannel MISFET Qp1 are thinner than the selecting MISFET Qs, the Nchannel MISFET Qn1, Qn2, the P channel MISFET Qp1 can further beconverted to shorter channels. The performance of the semiconductorintegrated circuitry can thus be further improved. In the case of themethod of manufacturing the gate insulating film in such a case, it ispossible to use the same method as that described in the fourthembodiment to form the gate insulating films of the flash memory areaand the DRAM area in different processes separately.

In addition, although a DRAM or a flash memory that is a nonvolatilememory is used as the memory cells in the first to fifth embodiments, anSRAM (Static RAM), a masked ROM, etc. may be used instead of those; forexample, a memory structure wherein a side wall spacer is put betweenword lines to connect each electric conductor to the source or the drainarea of the MISFET in a self-matching manner may be adopted as thememory cell structure.

(6th Embodiment)

FIG. 50(a) is a cross sectional view of the memory cell area of the DRAMin the first embodiment of the present invention. FIG. 50(b) is a crosssectional view of the peripheral circuit area. FIG. 51 is a top view ofthe DRAM memory cell area in this sixth embodiment. FIG. 52 is a crosssectional view of the DRAM memory cell area in this sixth embodiment.FIG. 52(a) is a cross sectional view taken along the line IIIa—IIIa inFIG. 51. FIG. 52(b) is a cross sectional view taken along the lineIIIb—IIIb in FIG. 51. In FIG. 51, some members are hatched or shown withbroken lines for easier observation. The line Ia—Ia in FIG. 51 indicatesa cut-off portion of the cross sectional view shown in FIG. 50(a).

In the DRAM memory cell area in the sixth embodiment, a memory cellselecting MISFET Qt is formed and a charge storage capacity element andbit lines BL connected to the selecting MISFET Qt are formed on the mainsurface of the semiconductor substrate 301.

In addition, in the DRAM peripheral circuit area there is formed ann-type MISFET Qn forming peripheral circuits. However, a p-type MISFET(not illustrated) is formed in a peripheral circuit, and the n-typeMISFET Qn and the p-type MISFET may be combined to form a CMISFET. Inaddition to the n-type MISFET Qn, a high withstand voltage n-type MISFET(not illustrated) may be formed.

The semiconductor substrate 301 is composed of, for example, p-typesilicon (Si) single crystal, and on the main surface there is formed ashallow groove 302 a. In addition, in the shallow groove 302 a there isembedded an element isolating insulating film 302 b composed of, forexample, silicon dioxide (SiO2) to form a shallow groove elementisolating area.

On the semiconductor substrate 301 there is also formed a p-type well303. In the p-type well 303 there is included, for example, boron, whichis a p-type impurity. Under the p-type well 303, in the area where amemory cell selecting MISFET Qt is formed, there is formed a deep well303 b. In the deep well 303 b, phosphorus is implanted, which is ann-type impurity, so that the selecting MISFET Qt is insulated from thesubstrate potential to improve the noise resistance of the circuitry.

When a p-type MISFET is formed, an n-type well (not illustrated) intowhich, for example, phosphorus is implanted, is formed in the area wherethe p-type MISFET is formed. In addition, in the p-type well 303 and inthe n-type well, if it exists, a MISFET threshold value control layer.

The memory cell selecting MISFET Qt is formed in an active areasurrounded by the element isolating insulating film 302 b. In an activearea there are formed two selecting MISFETs Qt. Each selecting MISFET Qthas gate electrodes 305 composed of a polycrystal silicon film 305 a anda tungsten silicide (WSi2) film 305 b formed on the semiconductorsubstrate 301 via the gate insulating film 304 formed in the active areaof the p-type well 303, and a pair of n-type semiconductor areas 306 aand 306 b formed on the p-type wells 303 on both sides of gateelectrodes 305, so as to be separated from each other.

Each gate electrode functions as a DRAM word line WL. Both n-typesemiconductor areas 306 a and 306 b are implanted with an n-typeimpurity, but the impurity may be either phosphorus or boron (As). Inorder to improve the withstand voltage between channels of the selectingMISFET Qt so as to improve the refreshing characteristics of the DRAM,however, phosphorus should preferably be implanted.

The n-type semiconductor area 306 a is shared by two selecting MISFETsQt. And, a channel area of the selecting MISFET Qt is formed between then-type semiconductor areas 306 a and 306 b. The gate insulating film 304is composed of, for example, SiO2. The film 304 may be thicker than thegate insulating film 304 of the n-type MISFET Qn of the peripheralcircuit area to be described later so that the dielectric strength ofthe selecting MISFET Qt is improved. In such a case, the dielectricstrength of the selecting MISFET Qt is improved so that the refreshingcharacteristics of the DRAM are improved.

On top of gate electrodes (word lines WL) THERE is formed a capinsulating film 307 b example, silicon nitride via an insulating film307 a. The cap insulating film 307 b functions as a blocking film whenopening the connecting holes 311 a and 311 b in a process to beexplained later in a self-matching matter with respect to the gateelectrodes 305. The cap insulating film 307 a prevents connectingmembers such as plugs from being short-circuited with gate electrodes305.

The surface of the cap insulating film 307 b, the side surfaces of eachgate electrode 305, and the main surface of the semiconductor substrate301 except for the bottoms of the connecting holes 311 a and 311 b arecovered respectively by an insulating film 309 for self-matchingtreatment composed of, for example, a silicon nitride film. Theinsulating film 309 functions as an etching stopper when the connectingholes 311 a and 311 b are opened in a self-matching manner with respectto the word lines, as well as to prevent the semiconductor substrate301, especially the element isolating insulating film 302 b, fromover-etching when the connecting holes 311 a and 311 b are opened.

At the phase boundary between the side surfaces of each of the gateelectrodes 305 and the insulating film 309 for self-matching treatmentthereof may be formed an insulating film (not illustrated). Such aninsulating film and the insulating film 307 a are provided to preventthe film forming apparatus from being contaminated with the metal thatmakes up the WSi film 305 b and to reduce the thermal stress on the capinsulating film 307 b and the insulating film 309 for self-matchingtreatment when the cap insulating film 307 b and the insulating film 309are formed.

The insulating film 309 for self-matching treatment is covered by aninterlaminar insulating film 310 a composed of, for example, SOG (SpinOn Glass). The interlaminar insulating film 310 a may be BPSG (BoronPhosphor Silicate Glass), but it should be a silicon oxide film that cansecure a proper etching selection ratio for silicon nitride films. And,in the interlaminar insulating film 310 a there are formed connectingholes 311 a from which the n-type semiconductor area 306 a formed as anupper layer of the semiconductor substrate 301 is exposed and connectingholes 311 b from which the n-type semiconductor area 306 b formed as anupper layer of the semiconductor substrate 301 is exposed.

The cap insulating film 307 b and the insulating film 309 forself-matching treatment can function as an etching stopper,respectively, as described above, when the connecting holes 311 a and311 b are opened in a self-matching manner. In addition, since theinsulating film 309 for self-matching treatment is formed and theconnecting holes 311 a and 311 b are opened in a two-stage etchingprocess (the first etching process being conditioned to make it easy toetch the interlaminar insulating film 310 a (etching depth and etchingspeed; larger) and not easy to etch the insulating film 309 forself-matching treatment (etching depth and etching speed; small) and thesecond etching process being conditioned to make it easy to etch theinsulating film 309 for self-matching treatment and not easy to etch theelement isolating insulating film 302 b), the element isolatinginsulating film 302 b formed up to the bottoms of the connecting holes311 a and 311 b is prevented from over-etching even when the bottoms ofthe connecting holes 311 a and 311 b are off the active area of thesemiconductor substrate 301 and overlap part of the element isolatinginsulating film 302 b, as shown in FIGS. 52(a) and FIG. (b). Thus, thebottoms of the connecting holes 311 a and 311 b do not reach the deeparea of the element isolating insulating film 302 b. In other words,even when the element isolating insulating film 302 b is etchedexcessively, the etching creates no problem for the process. Forexample, etching can be controlled equally to or under the thickness ofthe insulating film 309 for self-matching treatment.

In each connecting hole 311 b there is formed a plug 314 composed ofpolycrystal silicon in which, for example, phosphorus is implanted at ahigh density. At the bottom of the plug 314 there is formed an elementisolating insulating film 302 b even in an over-etched area. The etchingdepth is controlled to an extent to suppress problems in the process asdescribed above. Thus, the performance of the DRAM refreshingcharacteristics will not be affected by the etching depth at all.

On both the interlaminar insulating film 310a and on the plug 314 thereis formed an interlaminar insulating film 310 b. The interlaminarinsulating film 310 b maybe a silicon oxide film deposited by thethermal CVD method, for example, using TEOS (tetraethoxysilane).

On the interlaminar insulating film 310 b are formed bit lines BL. Thebit line BL is composed of a polycrystal silicon film 312 and a WSi2film 313 and is connected electrically to the n-type semiconductor area306 a via connecting holes 311 a. At the bottom of the polycrystalsilicon film 312 there is formed an element isolating insulating film302 b even in an over-etched area just like the plug 314, but theetching depth is controlled to an extent to suppress problems asdescribed above. Thus, the DRAM performance is not affected by theetching depth at all.

The bit lines BL are covered by an interlaminar insulating film 310 ccomposed of a silicon oxide film deposited by the thermal CVD method,for example, using TEOS. Furthermore, on the interlaminar insulatingfilm 310 c there is formed an interlaminar insulating film 310 d; whichis polished and flattened with the CMP method. The interlaminarinsulating film 310 d is formed with the CMP method by 20 polishing asilicon oxide film deposited with the plasma CVD method, for example,using TEOS. The interlaminar insulating film 310 d may be formed usingSOG or BPSG with the etch-back method, etc.

On the interlaminar insulating film 310 d there is formed an theinterlaminar insulating film 310 e composed, for example, of a siliconnitride film. The interlaminar insulating film 310 e is used as ablocking film when a crown-like storage capacity SN to be explainedlater is formed.

On the interlaminar insulating film 310 d there is formed a storagecapacity SN which is like a cylindrical crown in shape. The storagecapacity SN is composed of capacitor electrodes 320 a formed by thefirst electrodes 320 a connected to the n-type semiconductor area 306 bvia connecting holes 311 c and the second electrodes 320 d providedvertically to the semiconductor substrate 301; a capacitor insulatingfilm 321; and plate electrodes 322 connected to a specified wiringelectrically. The first and second electrodes 320 a and 320 b may be apolycrystal film in which, for example, phosphorus is implanted at ahigh density. The capacitor insulating film 321 may be a laminated filmformed by deposition on a silicon nitride film, but it may also be ahigh permittivity thin film, such as tantalum oxide. The plateelectrodes 322 may be a polycrystal silicon film in which, for example,phosphorus is implanted at a high density, but it may also be a metalliccompound such as tungsten silicide.

Under the first electrodes 320 a there are formed side walls 320 dcomposed of a polycrystal silicon film 320 c and a polycrystal silicon.The walls function as part of the capacitor electrodes 320. Thepolycrystal silicon film 320 c and the side walls 320 d also function asa hardware mask respectively for opening connecting holes 311 c anddetermine the diameter of each connecting hole 311 c to a fine degreeunder the resolution of the photolithography.

On the other hand, the n-type MISFET Qn of the peripheral circuit areais formed in an active area surrounded by the element isolatinginsulating film 302 b. The n-type MISFET is composed of gate electrodes305 composed of a polycrystal silicon film 305 a formed on thesemiconductor substrate 301 via a gate insulating film 304 formed in anactive area of the p-type well 303 and a WSi2 film 305 b; and a pair ofn-type semiconductor areas 306 c formed on both ends of the gateelectrodes 305 so as to be separated from each other.

The gate electrodes 305 are formed together with the word lines WL. Eachn-type semiconductor area 306 c includes a low density n-typesemiconductor area 306 c-1 and a high density n-type semiconductor area306 c-2 (higher density than the low density n-type semiconductor area306 c-1) formed in a self-matching manner with respect to the secondside walls 323 b. In other words, the n-type semiconductor area 306 chas a so-called LDD (Lightly Doped Drain) structure. And, between thehigh density n-type semiconductor area 306 c-2 formed under the lowdensity n-type semiconductor area 306 c-1 and the channel area there isformed a p-type semiconductor area 306 d that functions as apunched-through stopper. In the n-type semiconductor area 306 c there isimplanted, for example, phosphorus or arsenic. However, in order toshorten the channel length of the n-type MISFET Qn to improve theperformance, arsenic should be implanted. To form a high dielectricstrength type MISFET, phosphorus should be implanted in the low densityn-type semiconductor area 306 c-1. Consequently, the dielectric strengthbetween channels is improved.

The gate insulating film 304 is the same as that of the selecting MISFETQt, and so an explanation thereof will be omitted here.

Just like the selecting MISFET Qt described above, a cap insulating film307 b is also formed on top of each gate electrode 305 via an insulatingfilm 307 a. Thus, explanation thereof will also be omitted here.

On both side surfaces of each gate electrode 305, the first side walls323 a are formed, and outside the side walls 323 a, the second sidewalls 323 b are formed.

The first side walls 323 a are formed by anisotropic etching performedfor the insulating film 309 for self-matching treatment to be describedlater. For example, the first side walls 323 a are composed of a siliconnitride film. These first side walls 323 a can also be used as sidewalls for opening connecting holes in a self-matching manner withrespect to gate electrodes 305 when the connecting holes are formed inthe peripheral circuit area.

The second side walls 323 b are composed of, for example, a siliconoxide film and they are used as a mask for ion-implanting of impuritiesto form a high density n-type semiconductor area 306 c-2, so that thehigh density n-type semiconductor area 306 c-2 is formed in aself-matching manner. By controlling the thickness of this second sidewall film 323 b, the LDD structure can be optimized to improve theperformance of the n-type MISFET Qn.

As described above, the insulating film 309 for self-matching treatmenton the semiconductor substrate 301 is removed by anisotropic etching andthe insulating film for self-matching treatment 309 is not provided inthe peripheral circuit area. Thus, there is no need to open theconnecting holes in the peripheral circuit area in two stages,permitting the holes to be opened easily. When the gate electrodes 305in the peripheral circuit area are connected to a wiring in the upperlayer, the connecting holes can be opened easily. The reason why thereis no need to provide the insulating film for self-matching treatment309 in the peripheral circuit area can be explained as follows: theMISFET formed in the peripheral circuit area does not require such ahigh integration and so a rather large margin can be secured for thepitches of elements, as well as a margin can be secured for formingactive areas. Thus, failures in opening the connecting holes can betaken into consideration during design. When a high integration isrequired for the peripheral circuit area, therefore, the etching stopper104 described in the second embodiment may be formed selectively in theperipheral circuit area after the second side walls 323 b are formed, ofcourse.

When it is needed, a p-type MISFET can be formed in the sameconfiguration as that of the n-type MISFET Qn just by reversing theelectrical conductivity.

At the phase boundary between side surfaces of each gate electrode 305and the first side walls 323 a, an insulating film (not illustrated) maybe formed. Such an insulating film and the insulating film 307 a areprovided to prevent film forming apparatus from being contaminated withthe metal used for forming the WSi2 film 305 b and to reduce the thermalstress on the cap insulating film 307 b and the first side walls 323 awhen the cap insulating film 307 b and the first side walls 323 a areformed.

The n-type MISFET Qn is covered by an interlaminar insulating film 310 fcomposed of a silicon oxide film deposited by the CVD method using, forexample, TEOS. In addition, on the interlaminar insulating film 310 fthere is formed an interlaminar insulating film 310 g flattened by, forexample, the CMP method. The interlaminar insulating film 310 g may be asilicon oxide film deposited by the plasma CVD method using, forexample, TEOS. The interlaminar insulating film 310 g may be formed withSOG or BSPG and flattened using the etch-back method.

On the interlaminar insulating film 310 g there is formed theinterlaminar insulating film 310 b described above, and on theinterlaminar insulating film 310 b there is formed the bit lines BLdescribed above. The bit lines BL are covered by an interlaminarinsulating film 310 c described above, and on the interlaminarinsulating film 310 c there is formed the interlaminar insulating film310 d described above.

Both on the interlaminar insulating film 310 d and on the plateelectrodes 322 there is formed an interlaminar insulating film 324composed of, for example, BPSG. The interlaminar insulating film 324 isflattened by the reflowing method.

On the interlaminar insulating film 324 in the peripheral circuit areathere is formed the first wiring layer 325. The first wiring layer 325is connected to the high density n-type semiconductor area 306 c-2 ofthe n-type MISFET Qn via connecting holes 326. The first wiring layer325 may be a laminated film composed of a metallic film such as titannitride, titan, or aluminum. The laminated film may be deposited by, forexample, the spattering method. A plug composed of, for example,tungsten may be formed in each connecting hole 326. The tungsten plugmay be formed the tungsten CVD method. At this time, titan nitrideshould be used for forming a bonding layer beforehand in each connectinghole.

The first wiring layer 325 is covered by an interlaminar insulating film327, and on the interlaminar insulating film 327 there is formed thesecond wiring layer 328. The second wiring layer 328 is connected to thefirst wiring layer 325 via connecting holes 329. The interlaminarinsulating film 327 may be a silicon oxide film composed of, forexample, a silicon oxide film and SOG, but it should be a laminated filmformed by sandwiching the silicon oxide film between silicon oxide filmsdeposited by the plasma CVD method. The second wiring layer 328 shouldtake the same configuration as that of the first wiring layer 325.

The second wiring layer 328 is covered by an interlaminar insulatingfilm 330, and on the interlaminar insulating film 330 there is formedthe third wiring layer 331. The third wiring layer 331 is connected tothe second wiring layer 328 via connecting holes 332. The interlaminarinsulating film 330 may take the same configuration as that of theinterlaminar insulating film 327, and the third wiring layer 331 maytake the same configuration as that of the first wiring layer 325.

The third wiring layer 331 is covered by a passivation film 333. Thepassivation film 333 may be a laminated film composed of a silicon oxidefilm and a silicon nitride film.

Next, how to manufacture the DRAM will be described with reference toFIGS. 53(a) to 79(b).

FIGS. 53(a) to 79(b) are cross sectional views of a method ofmanufacturing the DRAM in this sixth embodiment in order of theprocesses. FIGS. 53(a) to 79(b) except for FIGS. 63(a) and (b), 65(a)and (b), 67(a) and (b), 69(a) and (b), and 71(a) and (b) indicate aportion equivalent to the cross sectional view taken along the lineIa—Ia shown in FIG. 51 in each (a) view and in each (b), view,respectively. They indicate a cross sectional view of the peripheralcircuit area. FIGS. 63(a), 65(a), 67(a), 69(a), and 71(a) indicate aportion equivalent to a cross sectional view taken along the lineIIIa—IIIa, and FIGS. 63(b), 65(b), 67(b), 69(b) and 71(b) indicates aportion equivalent to a cross sectional view taken along the lineIIIb—IIIb, shown in FIG. 51, respectively.

At first, as shown in FIG. 53(a) and FIG. 53(b), a shallow grooveelement, isolating area is formed in each specified area on thesemiconductor substrate 301. In the shallow groove element isolatingarea there is formed a silicon oxide film and a silicon nitride film(both not illustrated) sequentially on the main surface of thesemiconductor substrate 301. Then, both the silicon oxide film and thesilicon nitride film are removed by photo resist from the shallow groove302 a, and then a groove 0.3 to 0.4 μm in depth is formed in thesemiconductor substrate 301. Next, a silicon thermal-oxide film (notillustrated) is formed on surfaces of both the sides and bottom surfaceof the groove using the silicon nitride film as an oxidation mask. Then,a silicon oxide film is deposited all over the semiconductor substrate301 using the CVD (Chemical Vapor Deposition) method. The silicon oxidefilm is removed from the areas except for the shallow groove 302 a usingthe CMP (Chemical Mechanical Polishing) method or the dryetching methodto embed the silicon oxide film in the shallow groove 302 a selectively.

The element isolating insulating film 302 b should be densified in anatmosphere of oxidation. Then, the silicon nitride film is removed withheated phosphoric acid to form an element isolating insulating film 302b. At this time, the element isolating insulating film 302 b is slightlyetched with heated phosphoric acid so as to be lowered in positionrelative to the- active areas on the semiconductor substrate 301.Consequently, the gate electrodes 305 can be patterned moresatisfactorily to improve the performance of the MISFET.

As shown in FIG. 54(a) and FIG. 54(b), an n-type impurity, for example,phosphorus is ion-implanted in the memory cell array forming area on thesemiconductor substrate 301 using a photo resist as a mask. Then, thephoto resist is removed and a p-type impurity, for example, boron ision-implanted in the memory cell array forming area and the n-typeMISFET Qn forming area on the semiconductor substrate 301. The photoresist is then removed and a heat distribution treatment is performedfor the semiconductor substrate 301 to form a deep well 303 b and ap-well 303. To form a p-type MISFET, for example, phosphorus isimplanted in the area to form an n-well.

And, in order to optimize the impurity density in a channel area andobtain the threshold voltage of a desired memory cell selecting MISFETQt or an n-type MISFET Qn, a p-type impurity, for example, boron can beion-implanted in the main surface of the active area of the p-well 303.

As shown in FIG. 55(a) and FIG. 55(b), a gate insulating film 304 isformed on the surface of the semiconductor substrate 301. This gateinsulating film 304 is formed using the thermal oxidation method with athickness of about 7 nm. In addition, a polycrystal silicon film 305 aformed by implanting phosphorus all over the semiconductor substrate 301and a WSi₂ film 305 b are deposited sequentially. The CVD method is usedto form the polycrystal silicon film 305 a and the WSi₂ film 305 b. Theyare 40 nm and 100 nm in thickness, respectively. Then, on the WSi₂ film305 b an insulating film 307 a composed of a silicon oxide and a capinsulating film 307 b composed of a silicon nitride and depositedsequentially. The CVD method is used to form the insulating film 307 aand the cap insulating film 307 b. The films 307 a and 307 b are 10 nmand 160 nm in thickness, respectively.

As shown in FIG. 56(a) and FIG. 56(b), the gate electrodes 305 of theselecting MISFET Qt for the memory cells composed of a polycrystalsilicon film 305 a and a WSi₂ film 305 b and the peripheral circuitMISFET Qn are formed by etching a cap insulating film 307 b, aninsulating film 307 a, a WSi₂ film 305 b, a polycrystal silicon film 305a of an laminating film sequentially using photo resist as a mask.

Next, the photo resist is removed, and then a thermal oxidationtreatment is performed on the semiconductor substrate 301 to form a thinsilicon oxide film on the side surfaces of the polycrystal silicon film305 a formed by gate electrodes 305 and the WSi₂ film 305 b.

As shown in FIG. 57(a) and FIG. 57(b), a p-type impurity, for example,boron is ion-implanted in the main surface of the p-well in the areawhere an n-type MISFET Qn of the peripheral circuit area is formed usingthe laminated film described above and a photo resist as masks, and thenan n-type impurity, for example, arsenic is ion-implanted in the samemain surface. Furthermore, after the photo resist is removed, animpurity, for example, phosphorus is ion-implanted in the main surfaceof the p-well 303 where a selecting MISFET Qt is formed, using thelaminated film described above and a photo resist as masks. Then, thoseimpurities are expanded and distributed to form a low density n-typesemiconductor area 306 c-1 and a p-type semiconductor area 306 d of then-type MISFET Qn and n-type semiconductor areas 306 a and 306 b of theselecting MISFET Qt. To form a high dielectric strength n-type MISFET,phosphorus is implanted in the area. To form a p-type MISFET, arsenicfor a punched-through stopper and boron (BF₂) for a low densitysemiconductor area are implanted in the area. The low density n-typesemiconductor area 306 c-1 for the peripheral circuit MISFET Qn and then-type semiconductor areas 306 a and 306 b of the memory cell selectingMISFET Qt are formed in a self-matching manner with respect to the gateelectrodes.

As shown in FIG. 58(a) and FIG. 58(b), a silicon nitride film 334 isdeposited. The thickness of the silicon nitride film 334 can be, forexample, 80nm. Then, an SOG film 335 is deposited, and the memory arrayarea is masked with photo resist to etch the SOG film 335 and thesilicon nitride film 334. The etching may be anisotropic etching such asRIE (Reactive Ion Etching). Consequently, the SOG film 335 and thesilicon nitride film 334 are removed from the peripheral circuit area toform an insulating film for self-matching treatment 309 and aninterlaminar insulating film 310 a in the memory array area. Theinterlaminar insulating film 310 a is composed of SOG, so that the film310 a can fill each recess and flatten the surfaces of the gateelectrodes 305 and the cap insulating film 307 b. Furthermore, sinceanisotropic etching is performed, the first side walls 323 a composed ofa silicon nitride film are formed on side surfaces of the gateelectrodes 305 of the n-type MISFET Qn and the cap insulating film 307 bin the peripheral circuit area.

As shown in FIG. 59(a) and FIG. 59(b), a TEOS silicon oxide film (notillustrated) is formed all over the surface of the semiconductorsubstrate 301, and then the film is anisotropic-etched to form thesecond side walls 323 b on side surfaces of the first side walls 323 a.The second side walls 323 b should be thicker (wider) than the firstside walls 323 a. The memory cell can thus be divided finely and thecharacteristics of the peripheral circuit MISFET are improved.

As shown in FIG. 60(a) and FIG. 60(b), n-type impurities, for example,arsenic and phosphorus are ion-implanted in the peripheral circuit areawhere the n-type MISFET Qn is formed, using the gate electrodes 305, thecap insulating film 307 b, the second side walls 323 b, and a photoresist as masks. Then, the photo resist is removed and the impuritiesare expanded and distributed to form a high density n-type semiconductorarea 306 c-2 of the n-type MISFET Qn. To form a p-type MISFET, boron(BF₂) for a high density semiconductor area is implanted in the area.This high density n-type semiconductor area 306 c-2 is formed in aself-matching manner with respect to the second side walls 323 b.

As shown in FIG. 61(a) and FIG. 61(b), a TEOS silicon oxide film isdeposited to form an interlaminar insulating film 310 f. In addition, asilicon oxide film is deposited by the plasma CVD method using TEOS, andthen the silicon oxide film is flattened by CMP method (polishing) toform an interlaminar insulating film 310 g. In the memory cell portionthere is deposited a TEOS silicon oxide film 310 f and another siliconoxide film, while the SOG film 335 is left as it is. The surface isflattened using the CMP method. Thereafter, in the memory cell portionthe SOG film 335, the TEOS silicon oxide film 310 f, and the polishedsilicon oxide film remain. This 3-layer insulating film is referred toas an interlaminar insulating film 310 g.

Next, as shown in FIGS. 62(a) to 65(b), the interlaminar insulating film310 a is etched using a photo resist as a mask to form connecting holes311 b. The connecting holes 311 b are opened by etching performed in twostages.

At first, the first etching process is performed under conditions whichmake it easy to etch the silicon oxide film and not easy to etch thesilicon nitride film. Such etching is performed as an anisotropic plasmaetching using a mixed gas containing, f or example, C₄F₈ and argon asmaterial gases. In this first etching process, it is not easy to etchthe silicon nitride film, so etching of the interlaminar insulating film310 a composed of a silicon oxide is advanced into the stage in whichthe insulating film for self-matching treatment 309 composed of asilicon nitride film is exposed. FIGS. 62(a) and 63(b) indicate thisstate In other words, the insulating film for self-matching treatment309 functions as an etching stopper in the first etching process.

Next, the second etching process is performed under conditions whichmake it easy to etch the silicon nitride film. Such etching is performedas an anisotropic plasma etching using a mixed gas containing CHF₃, CF₄and argon as material gases. In the second etching process, it is onlynecessary to etch the thinner insulating film for self-matchingtreatment 309, since the thicker interlaminar insulating film 310 aalready has been removed in the first etching process. In other words,it is possible to etch the insulating film for self-matching treatment309 with an a sufficient process margin by suppressing over-etching tothe ground of the insulating film for self-matching treatment 309. Thismeans that under conditions which make it easy to etch silicon nitridefilms, no selection ratio of silicon nitride films to silicon oxidefilms can be taken. Thus, both silicon nitride and silicon oxide filmsare etched. As a result, as shown in FIG. 65(b), when the bottom of anyconnecting hole 311 b overlaps the element isolating insulating film 302b, the insulating film 302 b composed of a silicon oxide film is alsoetched. Ideally, the etching should be such that only the insulatingfilm for self-matching treatment 309 is etched and the etching is endedjust after the insulating film for self-matching treatment 309 isremoved. It is generally difficult, however, to open connecting holes311 b in every area on the substrate and perform a just-etching becauseof problems such as etching speed distribution on the substrate, etc.Over-etching cannot be avoided to a certain extent. When the bottom ofany connecting hole 311 b goes over an active area and overlaps theelement isolating insulating film 302 b, therefore, the insulating film302 b might be over-etched. In this method, however, the insulating filmfor self-matching treatment 309 is as thin as 80 nm, and it is necessaryto etch only the insulating film for self-matching treatment 309, sothat the over-etching will be sufficient if the depth reaches 30 to 50%of the thickness of the insulating film for self-matching treatment 309and at most the thickness of the insulating film for self-matchingtreatment 309. Overetching for the element isolating insulating film 302b can thus be minimized and the refreshing characteristics of the DRAMcan be improved significantly to improve the performance of the-DRAM.

In the second etching process, the gate electrodes 305 are covered byboth the insulating film for self-matching treatment 309 and the capinsulating film 307 b, as shown in FIG. 64(a) and FIG. 64(b), so thegate electrodes 305 are not exposed even when designed so that theconnecting holes 311 b overlap the gate electrodes 305. Connecting holes311 b can thus be opened in a self-matching manner. In other words, theinsulating film for self-matching treatment 309 can function to openconnecting holes 311 b in a self-matching manner with respect to gateelectrodes 305 and to suppress overetching of the element isolatinginsulating film 302 b.

In the two-stage etching method that uses the insulating film forself-matching treatment 309 in such a way, the degree of integration isimproved and if effective especially for a DRAM in which the intervalbetween gate electrodes 305 is narrow. In other words, when side wallsare formed on side surfaces of each gate electrode 305 for openingconnecting holes in a self-matching manner with respect to the gateelectrodes 305, if an attempt is made to form a stopper film to suppressover-etching of the element isolating insulating film 302 b, eachconnecting hole 311 b composing each space between gate electrodes 305is filled or even when the space is not filled, the bottom area of eachconnecting hole 311 b is minimized. And, this makes it difficult tosecure a sufficient connecting conductivity. In the case of themanufacturing method in the sixth embodiment, however, no side wall isformed for self-matching opening of connecting holes with respect togate electrodes 305. Instead, the insulating film for self-matchingtreatment 309 is provided with a function for such a self-matchingopening, so that a sufficient space can be secured between gateelectrodes 305 and the connecting reliability are assured while theprocess margin for opening connecting holes 311 b is maintained.

Next, as shown in FIGS. 66(a) and 67(b), a plug 314 is formed in eachconnecting hole 311 b. The plug 314 may be polycrystal silicon implantedwith phosphorus. The plug 314 can be formed by depositing a polycrystalsilicon film all over the surface of the semiconductor substrate 301 andetching-back the polycrystal silicon film. Since the bottom of theconnecting hole 311 b does not reach the depth of the element isolatinginsulating film 302 b, the bottom of the plug 314 is formed in a shallowarea even in an area where a connecting hole 311 b overlaps theinsulating film 302 b, so that the reliability of the DRAM is improved.

Next, as shown in FIGS. 68(b) and 69(b), an interlaminar insulating film310 b composed of a TOES silicon oxide film is formed all over thesemiconductor substrate 301, and then connecting holes 311 a are formed.The connecting holes 311 a can be formed in a two-stage etching processjust like the connecting holes 311 b. And, just like connecting holes311 b, a plug is not formed in the depth of the element isolatinginsulating film 302 b even in each connecting hole 311 a.

Next, as shown in FIGS. 70(a) and 71(a), a polycrystal silicon film 312implanted with phosphorus and a WSi2 film 313 are deposited sequentiallyusing the CVD method, and then the film is patterned to form bit linesBL. The bit lines BL are connected to one n-type semiconductor area 306a of the memory cell selecting MISFET Qt. Just like the plug 314, thebottom of the polycrystal silicon film 312 is formed in the shallow areaeven in the area where the connecting holes 311 a overlap the elementisolating insulating film 302 b. The reliability of the DRAM is thusimproved.

As shown in FIG. 72, on the semiconductor substrate 301 there isdeposited an interlaminar insulating film 310 c composed of a siliconoxide film and an interlaminar insulating film 310 d using the CVDmethod, and then the surface of the interlaminar insulating film 310 dis flattened using, for example, the CMP method. On the semiconductorsubstrate 3-1 there is formed an interlaminar insulating film 310 ecomposed of a silicon nitride film.

As shown in FIG. 73(a) and FIG. 73(b), a silicon oxide film 336 isdeposited, and then a polycrystal silicon film 320 c is deposited andpatterned using a photo resist as a mask. Furthermore, a polycrystalsilicon film (not illustrated) is deposited and anisotropic-etched toform side walls 320 d. Since side walls 320 d are formed in such a way,holes can be formed with a smaller diameter than those of thepolycrystal silicon film 320 c patterned with the minimum resolution oflithography.

As shown in FIG. 74(a), connecting holes 311 c, masked by thepolycrystal silicon film 320 c, and the side walls 320 d, are opened.

Then, as shown in FIG. 75(a) and FIG. 75(b), the first electrodes 320 aimplanted with phosphorus and a silicon oxide film 337 are depositedsequentially on it the semiconductor substrate 301. Each of the firstelectrodes 320 a is deposited in a connecting hole 311 c and connectedto a plug 314.

As shown in FIG. 76(a) and FIG. 76(b), the silicon oxide film 337 maskedby photo resist is etched, and then the first electrodes 320 a and thepolycrystal silicon film 320 c are etched sequentially. The treatedfirst electrodes 320 a and the polycrystal silicon film 320 c are usedas part of the storage capacity element for storing information in thememory cell area.

Next, the photo resist is removed, as shown in FIG. 77(b), and apolycrystal silicon film (not illustrated) is deposited on thesemiconductor substrate 301 using the CVD method. Then, anisotropicetching is performed for the polycrystal silicon film to form the secondelectrodes 320 b. Furthermore, the silicon oxide films 336 and 337 areremoved by wet etching using, f or example, an acid fluoride solution toform the first electrodes 320 a, the second electrodes 320 b, and thecrown-like capacitor electrodes 320 composed of a polycrystal siliconfilm 320 c and side walls 320 d.

As shown in FIG. 78(a), polycrystal silicon particles of about 40 nm indiameter are grown on each capacitor electrode 320, and then a siliconnitride film (not illustrated) is deposited on the semiconductorsubstrate 301 using the CVD method. An oxidation treatment is performedfor the film to form a silicon oxide film on the surface of the siliconnitride film and form a capacitor insulating film 321 composed of asilicon oxide film and a silicon nitride film on the surfaces of thecapacitor electrodes 320. Thereafter, on the semiconductor substrate 301there is deposited a polycrystal silicon film (not illustrated) usingthe CVD method and this polycrystal silicon film is masked with a photoresist and etched to form plate electrodes 322.

As shown in FIG. 79(a) and 79(b), a BPSG film is deposited and annealedto form an interlaminar insulating film 324. Then, the interlaminarinsulating film 324 is masked with a photo resist and etched to openconnecting holes 326. When the holes 326 are opened, the first sidewalls 323 a can be used to open the connecting holes 326 in aself-matching manner with respect to the gate electrodes 305 in theperipheral circuit area. Furthermore, titan, titan nitride, aluminum,and titan are deposited sequentially and patterned to form the firstwiring layer 325. On an inner surface of each connecting hole 326 theremay also be deposited titan to form a tungsten film using the CVDmethod, then the tungsten film is etched back to form a tungsten plug.The spattering method can be used for depositing titan nitride,aluminum, and titan.

Finally, a TEOS silicon oxide film is deposited using the plasma CVDmethod, and then an SOG film is coated on the film and a TEOS siliconoxide film is deposited on the film using the plasma CVD method to forman interlaminar insulating film 327. Just like the first wiring layer,connecting holes 329, the second wiring layer 328, the interlaminarinsulating film 330, connecting holes 332, and the third wiring layer331 are formed. Then, a TEOS silicon oxide film and a silicon nitridefilm are deposited on the surface using the plasma CVD method to form apassivation film 333. Thus, the manufacturing of the DRAM shown in FIG.50(a) and FIG. 50(b) is almost finished.

According to the DRAM in this sixth embodiment, since the insulatingfilm for self-matching treatment 309 is used to open the connectingholes 311 a and 311 b by two-stage etching, plugs 314 and bit lines BLcan be formed in a self-matching manner with respect to gate electrodes305, and the element isolating insulating film 302 bis prevented fromover-etching as well. The refreshing characteristics of the DRAM canthus be improved. In addition, no side wall is formed on the sidesurfaces of each gate electrode 305 in the memory cell area, so thatthis sixth embodiment can also cope with higher integration of the DRAM.

In addition, the insulating film for self-matching treatment 309 isprovided with two functions for forming self-matching contacts withrespect to the gate electrodes 305 and for preventing the elementisolating insulating film 302 b from over-etching, so that there is noneed to form a member for realizing each of the functions specially. Thenumber of processes can be reduced, thereby suppressing an increase inthe number of processes.

In this sixth embodiment, plugs 314 are used. However, no plug 314 needbe used, since the capacitor electrodes 320 may be connected to then-type semiconductor area 306 b directly via connecting holes 311 b. Inthis case, connecting holes 311 b are formed deeply, the etching marginbecomes small and treatment of those holes becomes difficult. When thetwo-stage etching in this sixth embodiment is used, however, the etchingmargin is increased and it becomes possible to cope with opening of theconnecting holes. In other words, when no plug 314 is used, the effectof the present invention becomes more clear.

Needless to say, the two-stage etching described above may also beperformed as continuous processes.

In FIG. 60(b), after a high density n-type semiconductor area 306 c-2 ofthe n-type MISFET Qn is formed, the silicon nitride film 104 shown inthe second embodiment is formed selectively in the peripheral circuitarea, and then the TEOS silicon oxide film shown in FIG. 61(b) isdeposited to form an interlaminar insulating film 310 f. The subsequentprocesses can also be performed.

After a high density n-type semiconductor area 306 c-2 of the n-typeMISFET Qn is formed as shown in FIG. 60(b), the third embodiment can beobtained.

In other words, after a high density n-type semiconductor area 306 c-2of the n-type MISFET Qn is formed, high melting-point metals such asmolybdenum and cobalt are deposited in the peripheral circuit area toform a silicide layer on the surface of the high density n-typesemiconductor area 306 c-2 of the n-type MISFET Qn for peripheralcircuits. Thereafter, non-reacted high melting-point metals are removedand a TEOS silicon film shown in FIG. 61(b) is deposited to form aninterlaminar insulating film 310 f. The subsequent processes can also beperformed.

The above examples can also be applied in the case of the seventh andeighth embodiments.

(7th Embodiment)

FIGS. 80(a), 80(b) and FIGS. 81(a), 81(b) are cross sectional viewsindicating a method of manufacturing the DRAM according to anotherembodiment of the present invention.

The method of manufacturing the DRAM in this seventh embodiment involvesthe same process as that in the sixth embodiment up to the forming ofthe gate electrodes 305 and the cap insulating film 307 b (FIG. 57(a)and FIG. 57(b)). The explanation will thus be omitted here, avoiding aredundant explanation.

The method of manufacturing the DRAM in this seventh embodimentindicates a case where the gate electrodes 305 in the memory array areaare disposed finely and the insulating film 309 for self-matchingtreatment is removed from the peripheral circuit area without using anymask.

After the gate electrodes 305 and the cap insulating film 307 b areformed, a silicon nitride film to be used as an insulating film forself-matching treatment 309 is deposited as shown in FIG. 80(b), andthen a silicon oxide film 339 is deposited on the film 309. In thememory array area, since the gate electrodes 305 are disposed finely asshown in FIG. 80(a), the recesses of the silicon oxide film 339 arefilled completely, so that the surface is flattened. On the other hand,the gate electrodes 305 are formed more thinly in the peripheral circuitarea as shown in FIG. 80(b) than in the memory array area, so anunevenness of those electrodes 305 will appear almost faithfully on thesurface of the film 339.

As shown in FIG. 81(a), the silicon nitride film 309 and the siliconoxide film 339 are etched by anisotropic etching. This etching isperformed under conditions which make it easy to etch silicon nitridefilms using, for example, a mixed gas of CHF₃, CF₄ and argon. In thememory array area, since the surf ace of the silicon oxide film 339 isflat, only the silicon nitride film 309 is etched both on the flatsurface of the silicon oxide film 339 and on the surface of the siliconnitride film 307 b. Consequently, in the memory array area, the siliconnitride film 309 is left on the main surface of the semiconductorsubstrate 301 and the film 309 functions as an insulating film 309 forself-matching treatment. On the other hand, in the peripheral circuitarea, the silicon nitride film 309 and the silicon oxide film 330 on themain surface of the semiconductor substrate 301 and the surface of thecap insulating film 307 b except for the side surfaces of the gateelectrodes 305 are etched. The silicon nitride film 309 and the siliconoxide film 330 are left only as the first side walls 323 a and thesecond side walls 323 b of the gate electrodes 305.

According to the method of manufacturing the DRAM in this seventhembodiment, the insulating film for self-matching treatment 309 isformed in the memory array area and at the same time the first andsecond side walls 323 a and 323 b can be formed on the side surfaces ofeach gate electrode in the peripheral circuit area even without usingphoto masks, etc. Thus, the process can be simplified.

Hereafter, the processes are the same as those shown in FIG. 60(a) andsubsequent process for in the sixth embodiment. The explanation willthus be omitted here, avoiding redundant explanation.

(8th Embodiment)

FIGS. 82(a) to 84(b) are cross sectional views indicating a method ofmanufacturing the DRAM according to another embodiment of the presentinvention.

The manufacturing method according to this eighth embodiment is the sameas that in the sixth embodiment up to forming of the gate electrodes 305and the cap insulating film 307 (FIG. 57(a) and FIG. 57(b)). Theexplanation for the same processes will thus be omitted here.

The manufacturing method according to this eighth embodiment representsa case where the gate electrodes 305 are disposed thinly in the memoryarray area and a mask is used to remove the insulating film forself-matching treatment 309 in the peripheral circuit area.

After the gate electrodes 305 and the cap insulating film 307 b areformed, a silicon nitride film to be used as an insulating film forself-matching treatment 309 is deposited to form a photo mask 340 in thememory array area.

Then, as shown in FIG. 83(a) and FIG. 83(b), the insulating film forself-matching treatment 309 masked by the photo mask 340 is etched byanisotropic etching. This etching is performed under conditions whichmake it easy to etch the silicon nitride film using a mixed gas of, forexample, CHF₃, CF₄, and argon Consequently, the first side walls 323 aare formed on side surfaces of each gate electrode 305 in the peripheralcircuit area.

Furthermore, the photo mask 340 is removed, and then a silicon oxidefilm 341 is deposited all over the surface of the semiconductorsubstrate 301.

As shown in FIG. 84, the silicon oxide film 341 may be etched byanisotropic etching on conditions to make it difficult to etch siliconnitride films using, for example, a mixed gas of C₄F. and argon.Consequently, the second side walls 323 b are formed on side surfaces ofthe gate electrodes 305 not only in the peripheral circuit area, butalso in the memory cell array area.

According to this manufacturing method, the insulating film forself-matching treatment 309 is removed from the peripheral circuit areaand the second side walls 323 b can be formed on side surfaces of thegate electrodes 305. And, as described in the sixth embodiment, thethickness of the second side walls 323 b can be adjusted to optimize theLDD structure.

The subsequent processes are the same as those shown in FIG. 60(a) andsubsequent processes for the sixth embodiment, and thus, explanation forthose processes will be omitted here, avoiding redundant explanation.

The invention is as described above with reference to variousembodiments, but the present invention is not limited only to thoseembodiments. Needless to say, the embodiments may be varied freely aslong as the substance of the present invention is not exceeded.

For example, although the element isolating area is provided in theshallow groove element isolating area in the sixth to eighthembodiments, the element isolating area may be composed of a thick fieldinsulating film formed by the LOCOS method. In the present invention,since the shallow groove of the shallow groove element isolating area isformed more sharply than a bird's beak of the field insulating film, thepresent invention, when applied to a shallow element isolating area thatwill be affected significantly even by a slight deviation fromconnecting holes, can obtain more remarkable effects. And, the sameeffect can also be obtained when the present invention is applied to anelement isolating area formed with a field insulating film, of course.

The present invention also includes the following features.

(1) The semiconductor integrated circuit of the present inventioncomprises a semiconductor substrate having an element isolating area andactive areas surrounded by the element isolating area respectively onits main surface; a gate insulating film formed on the main surface;gate electrodes formed on the gate insulating film; a cap insulatingfilm formed on the gate electrodes; a MISFET including a semiconductorarea formed in both active areas on both sides of the gate electrodes;and an interlaminar insulating film insulating the MISFET and aconductive member formed in the upper layer of the MISFET, wherein aninsulating film for self-matching treatment having an etching selectionratio for interlaminar insulating films is formed on the main surface ofthe semiconductor substrate including the top and side surfaces of thecap insulating film in all or part of the MISFET areas, as well as sidesurfaces of the gate electrodes, and the insulating film forself-matching treatment is used to open the holes for connecting theconductive member to the semiconductor area in a self-matching mannerwith respect to the gate electrodes and to prevent the bottom of eachconnecting hole going into the element isolating area off the activearea from over-etching.

According to the semiconductor integrated circuitry, since theinsulating film for self-matching treatment is formed on side surfacesof the gate electrodes and on the main surface of the semiconductorsubstrate so as to be used as side walls of the gate electrodes to openthe connecting holes in a self-matching manner and as a stopper film toprevent the element isolating area on the semiconductor substrate fromover-etching, the gate electrodes can be disposed at fine intervals toimprove the integration degree of the circuitry and especially to securea sufficient connecting area at the bottom of each connecting hole evenin every MISFET in the highly integrated DRAM memory mat area. As aresult, even in a highly integrated semiconductor integrated circuitry,self-matching contact technologies and over-etching preventivetechnologies for the element isolating area can be used together toimprove the integration degree and reliability of the semiconductorintegrated circuitry.

(2) In the semiconductor integrated circuitry, the insulating film forself-matching treatment can be formed adjacent to the side surfaces ofthe cap insulating film and the gate electrodes or via a thinner filmthan the insulating film for self-matching treatment. In addition, thereis no need to form any side wall among the insulating film forself-matching treatment, the side surfaces of the cap insulating film,and the gate electrodes. This is because the insulating film forself-matching treatment can be used as the side walls of each gateelectrode. Consequently, the margin for opening each connecting hole canbe increased and the process can be simplified to minimize an increaseof processes.

(3) In addition, the insulating film for self-matching treatment may bea silicon nitride film and each interlaminar insulating film may be asilicon oxide film. And, since the silicon nitride film and the siliconoxide film used frequently in the manufacturing processes ofconventional semiconductor integrated circuits, the solid stateproperties of those films are well known. It is thus possible to designprocesses and select conditions using existing established manufacturingprocesses to start up production processes speedily.

(4) In addition, the element isolating area can be formed in the shallowgroove element isolating area structured to isolate each element fromothers in a shallow groove or in the element isolating area having athick field insulating film formed with the selective oxidation method.Especially, in the case of the shallow groove element isolating area,the area is formed to rise sharply at a boundary between an active areaand the element isolating area, so an over-etched portion formed in theelement isolating area due to a slight deviation during the formation ofconnecting holes is deepened more than the thick field insulating film,so that the over-etching problem caused by such a deviation describedabove arises remarkably. When the present invention is applied to asemiconductor integrated circuit having a shallow groove elementisolating area to prevent the element isolating area from over-etching,therefore, the effect appears more remarkably.

(5) In addition, the semiconductor integrated circuit of the presentinvention includes a DRAM memory mat area and the insulating film forself-matching treatment is formed only in the DRAM memory mat area. Inother words, the insulating film for self-matching treatment is formedonly in the memory mat area that must be highly integrated to assurehigh integration and high reliability thereof And, the insulating filmfor self-matching treatment is not formed in other areas, including theperipheral circuit area, which are not needed to be highly integrated somuch.

According to the present invention, since a high integration and a highreliability are assured in the memory mat area, and no insulation filmfor self-matching treatment is formed in other areas including theperipheral circuit area, the process for forming holes connecting awiring layer formed together with the gate electrodes to the upper layerof the wiring layer or the process for forming holes connecting theMISFET semiconductor area in the peripheral circuit area to the upperlayer of the semiconductor area can be simplified. In other words, whenan insulating film for self-matching treatment is also formed in theperipheral circuit area, a two-stage etching process is needed foretching the insulating film for self-matching treatment when the holesconnecting the semiconductor area to the upper layer, as well as the capinsulating film formed on top of the gate electrodes and the insulatingfilm for self-matching treatment must also be etched when the holesconnecting the wiring layer formed together with the gate electrodes tothe upper layer are formed, resulting in a complicated process. Inaccordance the present invention, however, since no insulating film forself-matching treatment is formed in the peripheral circuit area, theprocess is not complicated.

(6) In addition, the semiconductor integrated circuit of the presentinvention includes a DRAM memory mat area, and on side surfaces of eachMISFET gate electrode formed in areas other than the memory mat areathere are formed side walls via an insulating film deposited in the sameprocess as that of the insulating film for self-matching treatment or incontact with the side surfaces of the insulation film.

According to the present invention, the LDD (Lightly Doped Drain) ofeach MISFET formed in areas other than the memory mat area can beoptimized to shorten the channel of the MISFET in areas other than thememory mat area and improve the performance.

The method of manufacturing the semiconductor integrated circuit of thepresent invention includes (a) a process for forming an elementisolating area on the main surface of a semiconductor substrate; (b) aprocess for depositing a silicon oxide film, serving as a gateinsulating film, a conductor film composed mainly with a polycrystalsilicon film, serving as gate electrodes, and a silicon nitride film,serving as a cap insulating film sequentially to form a laminated filmcomposed of those films all over the surface of the semiconductorsubstrate, then patterning the laminated film to form a gate insulatingfilm, gate electrodes, and a cap insulating film; (c) a process forforming a semiconductor area in an active area on the main surface ofthe semiconductor substrate, surrounded by the element isolating area byimplanting impurities using the gate electrodes as a mask; (d) a processfor depositing an insulating film for self-matching treatment all overthe surface of the semiconductor substrate; (e) a first etching processfor depositing an interlaminar insulating film all over the surface ofthe semiconductor substrate on which the insulating film forself-matching treatment is formed; (f) a process for etching theinterlaminar insulating film under conditions which make the etching ofthe insulating film for self-matching treatment slower than the etchingof the interlaminar insulating film selectively, and open part of theconnecting holes in a self-matching manner with respect to the gateelectrodes; and (g) a second etching process for performing anisotropicetching for the insulating film for self-matching treatment at thebottom of each connecting hole.

According to the method of manufacturing the semiconductor integratedcircuit, since the insulating film for self-matching treatment isdeposited without forming side walls after the gate electrodes and thecap insulating film are formed, a sufficient contact margin between gateelectrodes can be obtained. As a result, the reliability of thesemiconductor integrated circuitry in connecting the member formed ineach connecting hole to the semiconductor area formed in an active areacan be improved significantly.

In addition, since connecting holes are opened in two stages (the firstand second etching processes), the connecting holes can be opened in aself-matching manner with respect to the gate electrodes, and theelement isolating area going into the bottom of each connecting hole canbe prevented from over-etching as well. Consequently, the integration ofthe semiconductor integrated circuitry is improved and thecharacteristics of the MISFET of the semiconductor integrated circuitryis improved to improve the reliability. The first and second etchingprocesses in the two-stage etching can be continued processes, ofcourse.

(8) In addition, in order to form the element isolating area in theprocess (a), any of a first configuration in which a shallow groove isformed, then the shallow groove is covered by a silicon oxide film andthe surface is polished by etching-back or by the CMP method to leavethe silicon oxide film only in the shallow groove, or a secondconfiguration in which a thick field insulating film formed with thethermal oxidation method selectively using a patterned silicon nitridefilm as a mask, can be taken. According to the manufacturing method ofthe present invention, it is possible to easily manufacture asemiconductor integrated circuit having a shallow groove elementisolating area or a thick field insulating film formed by the LOCOSmethod.

(9) In addition, in the method of manufacturing the semiconductorintegrated circuitry of the present invention, the insulating film forself-matching treatment may be a silicon nitride film and theinterlaminar insulating film may be a silicon oxide film. The etching inthe first etching process may be plasma etching using a mixed gas OfC₄F₈ and argon and the etching in the second etching process may beplasma etching using a mixed gas of CHF₃, CF₄, and argon.

According to the manufacturing method of the present invention, sinceplasma etching is performed using a mixed gas of C₄F₈ and argon in thefirst etching process, the silicon oxide film can be etched underconditions which make it difficult to etch silicon nitride films, thatis, the silicon oxide film can be etched under conditions which canprovide a sufficient etching selection ratio for silicon nitride films.In addition, the interlaminar insulating film in the connecting holearea can be etched with a sufficient treatment margin up to theinsulating film for self-matching treatment formed on the main surfaceof the semiconductor substrate. The insulating film for self-matchingtreatment functions as a stopper film. In the second etching process,plasma etching can be performed using a mixed gas of CHF₃, CF₄, andargon, so the insulating film for self-matching treatment, composed of asilicon nitride film, can be etched easily. And, since only acomparatively thin silicon nitride film is etched in the second etchingprocess, the connecting holes can be opened with a sufficient margin andaccordingly, the element isolating area can be prevented fromover-etching effectively as described above.

(10) The method of manufacturing the semiconductor integrated circuitryof the present invention applies over-etching in the second etchingprocess so that the etching time is reduced in comparison to the timenecessary for etching the total thickness of the insulating film forself-matching treatment.

Such over-etching is possible because the insulating film forself-matching treatment is used as a stopper film opening of theconnecting holes by two-stage etching. And, because of the over-etchingapplied, connecting holes can be opened surely while active areas areetched slightly. The connecting reliability at the bottom of each holecan be improved. The etching depth in active areas is equal to thethickness of the insulating film for self-matching treatment or less,since the over-etching time is less than the time necessary for etchingthe total thickness of the insulating film for self-matching treatment.In addition, since the insulating film for self-matching treatment canbe as thinned to 30 to 50 nm , the over-etching creates no problem fromthe etching process.

(11) The method of manufacturing the semiconductor integrated circuitryof the present invention allows the DRAM memory mat area to be includedin the semiconductor integrated circuitry, and the method includes aprocess for forming side walls on side surfaces of the gate electrodesin areas other than the memory mat area and the cap insulating film withthe insulating film for self-matching treatment disposed therebetweenafter the insulating film for self-matching treatment is deposited.

According to the manufacturing method of the present invention, a properLDD structure can be formed in every MISFET other than in the memory matarea. As a result, the channel of every MISFET in areas other than thememory mat area, for example, the channel of the MISFET in theperipheral circuit area, can be shortened to improve the performance ofthe MISFET. And, since it is possible to generally take a margin for theinterval between gate electrodes in the peripheral circuit area, sidewalls can be formed on side surfaces of each gate electrode in theMISFET in the peripheral circuit area even when the insulating film forself-matching treatment is formed there.

(12) In addition, the method of manufacturing the semiconductorintegrated circuitry of the present invention allows the DRAM memory matarea to be included in the semiconductor integrated circuit, and themethod includes a process for removing the insulating film forself-matching treatment at least on the main surface of thesemiconductor substrate except for the memory mat area after theinsulating film for self-matching treatment is deposited.

According to the manufacturing method of the present invention, sincethe method includes a process for removing the insulating film forself-matching treatment from the main surface of the semiconductorsubstrate except for at least the memory mat area, it is possible toremove, for example, the insulating film for self-matching treatmentfrom the peripheral circuit area of the DRAM. Thus, it is possible toeasily open the connecting holes connected to the MISFET semiconductorarea or the gate electrodes in the peripheral circuit area.

(13) Side walls can be formed after the insulating film forself-matching treatment is deposited by etching the insulating film forself-matching treatment using the photo resist covering the memory matarea as a mask, and then by removing the photo resist, depositing aninsulating film all over the semiconductor substrate and anisotropicetching the insulating film. The etching of the insulating film forself-matching treatment may be anisotropic etching leaving theinsulating film for self-matching treatment on side surfaces of eachgate electrode as side walls or isotropic etching not leaving theinsulating film for self-matching treatment as side walls.

In addition, side walls can be formed after the insulating film forself-matching treatment is deposited by depositing an insulating filmthat covers uneven portions caused by the gate electrodes and the capinsulating film formed in the memory mat area on the insulating film andetching the insulating film by anisotropic etching. In such a case,since the insulating film fills each space between the gate electrodesin the memory mat area, the insulating film for self-matching treatmentformed on the main surface of the semiconductor substrate, between thegate electrodes in the memory mat area, is not etched by the anisotropicetching performed later. On the other hand, the insulating film forself-matching treatment in areas other than the memory mat area, forexample, in the peripheral circuit area, can be etched together with theinsulating film used for forming side walls in the anisotropic etching,since it is possible to take a margin for the interval between gateelectrodes in the peripheral circuit area. In other words, it ispossible to omit the mask forming process for etching only theinsulating film for self-matching treatment in the peripheral circuitarea. The process can thus be simplified.

Of those features described above, the effects obtained byrepresentative aspects of the invention can be summarized as follows.

(1) Connecting holes can be formed in a self-matching manner even in thehighly integrated DRAM memory cell area, and the element isolating areaat the bottom of each connecting hole can be prevented from over-etchingas well.

(2) When connecting holes are formed in a self-matching manner and theelement isolating area at the bottom of each connecting hole isprevented from over-etching, the treatment margin of the connectingholes can be improved.

(3) When connecting holes are formed in a self-matching manner and theelement isolating area at the bottom of each connecting hole isprevented from over-etching, an increase in the number of processes canbe suppressed.

(4) The integration degree of the semiconductor integrated circuitry isfurther improved, and the refreshing characteristics of the DRAM areimproved to improve the transistor characteristics of the memory cellarea as well.

According to the investigation of well-known examples carried out by thepresent inventor after the present invention was made, it was found thatthe technologies for forming connecting holes of one of the electrodesof a capacitor and forming bit line connecting holes in a self-matchingmanner with respect to word lines were disclosed in the public report ofUnexamined Published Japanese Invention Application No. 4-342164.

The technology for providing a silicon nitride film to prevent thesemiconductor substrate or the element isolating insulating film fromover-etching during the opening of both connecting holes of a capacitorand connecting holes of bit lines of one of the electrodes with respectto an interlaminar insulating film is disclosed in the public reports ofUnexamined Published Japanese Patent Application No. 8-264075 and No.8-344906. In addition, the technology for providing a silicon nitridefilm when connecting holes are opened to a source or a drain withrespect to an insulating film on an MOSFET is disclosed in the officialreport of Unexamined Published Japanese Patent Application No. 6-53162.

In addition, a method of manufacturing a semiconductor device having adouble side wall film composed of a silicon nitride film and a siliconoxide film on side walls of each gate electrode is disclosed in theofficial reports of Unexamined Published Japanese Patent Application No.3-276729 and No. 6-168955, as well as U.S. Pat. No. 5,364,804.

As described above, the semiconductor integrated circuitry and themethod of manufacturing the circuitry of the present invention aresuitable for fine treatment, high integration, and high reliability.Especially, the present invention is suitable for a DRAM, anelectrically reloadable nonvolatile memory or a highly integratedsemiconductor circuitry provided with a logic circuit, a DRAM, or anelectrically reloadable nonvolatile memory.

What is claimed is:
 1. A method of manufacturing a semiconductorintegrated circuit having memory cells, in each of which a first MISFETand a capacity element are connected serially; and a peripheral circuitcomprised of second MISFETS, comprising the steps of: (a) preparing asemiconductor substrate having a first area for forming said memorycells and a second area for forming said peripheral circuit; (b) forminga first conductor layer on said semiconductor substrate and a firstinsulating film on said a first conductor layer; (c) forming firstMISFET gate electrodes in said first area and second MISFET gateelectrodes in said second area by patterning said first conductor layerand first insulating film; (d) implanting first conduction type impurityto form a first semiconductor area in a self-matching manner withrespect to said second gate electrodes in said second area; (e)depositing a second insulating film covering said first and second gateelectrodes; (f) forming first side wall spacers on side surfaces of saidsecond gate electrodes in said second area by performing anisotropicetching of said second insulating film; (g) depositing a thirdinsulating film in said second area so as to cover said second gateelectrodes and first side wall spacers; (h) forming second side wallspacers on side surfaces of said first side wall spacers in said secondarea by performing anisotropic etching of said third insulating film;(i) implanting a first conduction type impurity to form a secondsemiconductor area in the second area in a self-matching manner withrespect to said second side wall spacers; (j) depositing a fourthinsulating film in said first area; (k) forming openings in said firstarea so as to overlap said first gate electrodes at some of saidopenings and expose the main surface of said semiconductor substrate;and (l) forming a second conductor layer in each of said openings insaid first area, wherein said second conductor layer and said first gateelectrodes are isolated electrically by said second insulating film fromeach other.
 2. A method of manufacturing a semiconductor integratedcircuit, as defined in claim 1, wherein said second insulating film andthird insulating film are formed with different members from each other.3. A method of manufacturing a semiconductor integrated circuit, asdefined in claim 2, wherein between steps (e) and (f) there is provideda step of forming a masking layer to cover said first ares selectively,and no anisotropic etching is performed on said second insulating filmin said first area in said process (f).
 4. A method of manufacturing asemiconductor integrated circuit, as defined in claim 3, wherein saidsteps (f) to (i) are performed while leaving said masking layer as is.5. A method of manufacturing a semiconductor integrated circuit, asdefined in claim 3, wherein said step (k) includes; (m) etching saidfourth insulating film under conditions determined so that said fourthinsulating film is etched more than said first insulating film; and (n)etching said first insulating film under conditions determined so thatsaid first insulating film is etched more than said semiconductorsubstrate or said fourth insulating film.
 6. A method of manufacturing asemiconductor integrated circuit as defined in claim 5, wherein betweensaid steps (a) and (b) there is further provided a step of forming anelement isolating area on the surface of said semiconductor substrate.7. A method of manufacturing a semiconductor integrated circuit, asdefined in claim 6, wherein said process for forming said elementisolating area includes: forming a groove on the surface of saidsemiconductor substrate; and filling said groove selectively with afifth insulating film.
 8. A method of manufacturing a semiconductorintegrated circuit, as defined in claim 3, wherein after said fourthinsulating film is formed, the surface of said fourth insulating film ispolished.
 9. A method of manufacturing a semiconductor integratedcircuit, as defined in claim 1, wherein in said step (f) there is alsoformed first side wall spacers on side surfaces of said first gateelectrodes in said first area.
 10. A method of manufacturing asemiconductor integrated circuit, as defined in claim 9, wherein saidstep (k) is performed under conditions determined so that said fourthinsulating film is etched more than said second insulating film.
 11. Amethod of manufacturing a semiconductor integrated circuit, as definedin claim 10, wherein said second insulating film is a silicon nitridefilm and said fourth insulating film is a silicon oxide film.
 12. Amethod of manufacturing a semiconductor integrated circuit, as definedin claim 11, wherein another process for polishing said fourthinsulating film is carried out after said fourth insulating film isformed.
 13. A method of manufacturing a semiconductor integrated circuithaving memory cells, in each of which a first MISFET and a capacityelement are connected serially, and a peripheral circuit comprised of asecond MISFET, comprising the steps of: (a) preparing a semiconductorsubstrate having a first area for forming said memory cells and a secondarea for forming said peripheral circuit; (b) forming a first conductorlayer on said semiconductor substrate and a first insulating film onsaid first conductor layer; (c) patterning said first conductor layerand first insulating film to form first MISFET gate electrodes in saidfirst area and second MISFET second gate electrodes in said second area;(d) implanting a first conduction type impurity to form a firstsemiconductor area in said second area in a self-matching manner withrespect to said second gate electrodes; (e) depositing a secondinsulating film so as to cover said first and second gate electrodes;(f) performing anisotropic etching for said second insulating film insaid second area to form first side wall spacers on side surfaces ofsaid second gate electrodes; (g) depositing a third insulating film insaid second area so as to cover said second gate electrodes and firstside wall spacers; (h) performing anisotropic etching for said thirdinsulating film to form second side wall spacers on side walls of saidfirst side wall spacers in said second area; (i) implanting a firstconduction type impurity to form a second semiconductor area in aself-matching manner with respect to said second side wall spacers insaid second area; (j) depositing a high-melting point metal on thesurface of said second semiconductor area in said second area; (k)performing a thermal treatment on the surface of said secondsemiconductor area to form a high-melting metallic silicide layerthereon; (l) removing a non-reacted high-melting point metal; (m)depositing a fourth insulating film in said first area; (n) formingopenings in said first area so that some of said openings overlap onsaid first gate electrodes and part of the main surface of saidsemiconductor substrate is exposed; and (o) forming a second conductorlayer in each of said openings in said first area, wherein said secondconductor layer and said first gate electrodes are isolated by saidsecond insulating film electrically.